A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

“…It can be seen from Table 1 that, the TMR latch is only SNUtolerant, but the LCQNUSR latch can additionally provide SNU recovery. Although the authors of the paper in [9] claimed the QNU recovery of their proposed LCQNUSR latch, comprehensive validations demonstrate that the latch cannot even tolerate a DNU (e.g., a DNU on node pair <N1, N3>). The DNURL latch is not only SNU/DNU-tolerant but also SNU/DNU-resilient, but it cannot tolerate TNUs.…”

“…To tolerate soft errors in the device level, many storage cells, such as latches [2][3][4][5][6][7][8][9][10][11][12], SRAMs [13][14], and flip-flops [15][16], have been proposed. This paper focuses on latch designs.…”

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

“…Figure 3-(b) shows the schematic of SHLR [20], which consists of two CG-based 2-input CEs and three input-splitting inverters, forming feedback interlocking loops to recover the original values after a radiation event. An SHLR latch can tolerate and [20], (c) HLDTL-EV [21], (d) DNUSH [22], (e) TNULH [13], (f) TNURL [14], (g) QNUTL [15], (h) Quad-SIRI [16], (i) HLMR [17] and (j) LCQNUSR [18]. self-recover from SNU.…”

“…HLMR can tolerate QNU, but cannot recover from QNU. Figure 3-(j) shows the schematic of LCQNUSR [18], which is composed of six TGs, six inverters, and six CG-based 4input CEs. In [18], the author claimed that the latch can recover from QNU.…”

“…Therefore, in order to provide highly reliable integrated circuits, it is necessary to design storage cells that can tolerate and even recover from MNU. To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14].…”