A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

Chien, Feng-Tso; Hsueh, Kuang Po; Hong, Zhen Jie; Lin, Kuan-Ting; Tsai, Yuo-Tern; Chiu, Hsien Chin

doi:10.3390/coatings9080514

Cited by 4 publications

(2 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several methods have already been proposed for lower leakage current and higher performance [18][19][20][21][22][23][24][25][26][27][28][29][30] including field-induced drain (FID) [28,29] and current and electric field split (CES) design TFTs [30]. However, both FID and CES design TFTs suffer from complex fabrication process and large parasitic capacitance because they need one more field plate.…”

Section: Introductionmentioning

confidence: 99%

LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension

et al. 2020

View full text Add to dashboard Cite

A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little on-current loss. The amorphous silicon buffer layer having large bandgap energy (Eg) suppresses both thermal generation and minimum leakage current, which leads to higher on/off current ratio. In addition, the formation of lightly doped region near the drain alleviates the field-enhanced generation in the off-state by reducing electric field. TCAD simulation results show that the proposed TFT shows more than three orders of magnitude lower off-current than low-temperature polycrystalline silicon (LTPS) TFTs, while maintaining on-current.

show abstract

Section: Introductionmentioning

confidence: 99%

LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension

et al. 2020

View full text Add to dashboard Cite

show abstract

“…Low-temperature polycrystalline silicon (LTPS) has a long-range order. LTPS TFTs can exhibit a significantly higher µ and superior reliability [6][7][8]. In addition to n-type TFTs, p-type TFTs can also be realized using LTPS technology [8,9].…”

Section: Introductionmentioning

confidence: 99%

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Hsu¹,

Li²,

Chen³

et al. 2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.

show abstract