A low-jitter timing generator based on completely on-chip self-measurement and calibration in a field programmable gate array

Abstract

This paper presents a high-stability and low-jitter Arbitrary Timing Generator (ATG) design based on the Xilinx Field Programmable Gate Array (FPGA) and its special integrated delay line. In recent years, FPGA-based or application specific integrated circuit-based delay lines have been used to achieve picosecond-level timing resolution. Devices with pure digital delay methods can only acquire triggers at the clock rising edges when triggered externally. Therefore, there is a large time irregularity caused by the uncertainty of the entry time of the trigger, which is difficult to compensate and leads to a large time jitter of outputs. We describe the design of an ATG that includes jitter self-measurement and calibration methods, which is available for both internal and external trigger modes. This structure is completely based on the FPGA’s own resources and has the advantages of being simple and flexible. Experimental results show a sub-nanosecond timing resolution of 78 ± 20 ps with a minimum of 120 ps and a time jitter of 160 ± 20 ps in the external trigger mode after compensation.

An Integrated Dual-Mode Pulse-Echo Ultrasonic Measurement System Under Pulsed/Static Magnetic Field

“…According to the demands of precision, stability and flexibility of controller, this paper proposes a dual-mode ultrasonic measurement control system, which contains a multi-channel timing system, and a data acquisition & automatic analyzing system. The FPGA based multi-channel ultrasonic timing system is the extension and upgrading of our previous works [17] with a timing resolution of 5 ns/78 ps (for the Req.1), a timing range of 5 ns~21.5 s (for the Req.2) can be realized, and a timing jitter in external trigger mode within 160 ps (for the Req.4). Attached by a configurable offset-chain, it can be much easier to make the position of the sampling window consistent with the positions of ultrasonic echoes and reduce the data size by more than 80%, extending the maximum duration of ultrasonic experiments in pulsed field for 2 seconds or stable field for several hours (for the Req.3).…”

“…To keep the accuracy of excitation generating control and sampling window adjustment, a carry-chain based time-digital converter (TDC) + IDELAYE2 based digital-time converter (DTC)" (⑥ and ⑦ in Fig. 3) structure [17] is used to timely figure out the jitter size and carry out the compensation. The timing sequence diagram of the complete delay process is shown in Fig.…”

“…The "counter + IDELAYE2" based two-stage interpolation timing generation module in FPGA has been tested by both simulation and board-level verification. Experiments have been done in our previous research [17] and the results show that the timing generator can reach a resolution of 5 ns by the first stage for the excitation control, and a higher precision of 78 ps by the second stage for the adjustment of the sampling window. And previous long-term tests [17] show that the jitter of this timing system can maintain within 160 ps when the environment changes or the time courses.…”

Realisation of the reconfigurable pulsed high magnetic field facility and its scientific application at Wuhan National Pulsed High Magnetic Field Centre

“…An isolated fibre ethernet is employed for high‐speed communication between the two parts. The central control part mainly consists of a server, a timing signal generator [22] and a global emergency stop module [23]. The local control part is responsible for fulfiling local operations of the power modules and experiment stations [24].…”