A low‐latency memory‐cube network with dual diagonal mesh topology and bypassed pipelines

Abstract

SummaryA memory cube network is an interconnection network composed of 3D stacked memories called memory cubes. By exploiting a packet switching, it can provide fast memory accesses to a large number of memory cubes. Although interconnection networks have been studied in many years for supercomputers and data centers, existing technologies are difficult to apply to memory cube networks. This is because the link length and the number of ports are limited, and hence the hop count increases. In this article, we propose a dual diagonal mesh (DDM), a layout‐oriented memory‐cube network. Furthermore, we propose the routing algorithm and the router architecture with bypassed pipelines for DDM. Our experimental results demonstrate that our routing and router architecture with bypassed pipelines reduces the memory access latency. We implement four router architectures and evaluate them with the traffic patterns derived from the NAS parallel benchmark.