A Low-Loss 50–70 GHz SPDT Switch in 90 nm CMOS

Uzunkol, Mehmet; Rebeiz, Gabriel M.

doi:10.1109/jssc.2010.2057950

Cited by 99 publications

(56 citation statements)

References 14 publications

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“…1(b) and explained in detail below. The switching biases are different than most transmit/receive switches [3,4,5,6,7,8,9,10,11]. In these conventional switches, the switching transistors are biased either at 0 or 1 V. For the proposed work, in TX mode, the PA transistor gate biases are set to 0.7 V considering gain and linearity of TX whereas the LNA gate biases are 0 V. For both LNA and PA transistors drain voltage is 1 V either for ON or OFF cases.…”

Section: Proposed Integrated Antenna Switchmentioning

confidence: 99%

“…Transmit/receive switch for a mm-wave multiGb/s system is an advantageous block when considering phased array and multiinput multi-output (MIMO) communication for sharing antennas [3,4,5,6,7,8,9,10,11]. It is crucial to decrease the silicon area consumption of switch, while, also, care should be taken for noise figure (NF) of receiver (RX), and linearity of transmitter (TX).…”

Section: Introductionmentioning

confidence: 99%

“…It is crucial to decrease the silicon area consumption of switch, while, also, care should be taken for noise figure (NF) of receiver (RX), and linearity of transmitter (TX). Although there are other topologies for switch architecture [3,10,11], the common topology for antenna switch is based on quarter-wavelength (=4) [4,5,6,7,8]. The conventional switches has long =4 length (typically 600 to 700 µm in standard CMOS) transmission lines (TLs) which consumes relatively large area on-chip and introduce loss especially in mm-wave frequency region.…”

Section: Introductionmentioning

confidence: 99%

“…The conventional switches has long =4 length (typically 600 to 700 µm in standard CMOS) transmission lines (TLs) which consumes relatively large area on-chip and introduce loss especially in mm-wave frequency region. For instance, the switch in [5] has one of the best performance in terms of loss in the literature. However, the area of the switch is 0.275 mm 2 and for an 8 Â 8…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

Tokgoz

Kawai

Okada

et al. 2018

IEICE Electron. Express

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A 60 GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage's transistor of power amplifier (PA) and the first stage's transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 dB minimum noise figure (NF) in the receiver mode is measured, and 2 dBm of OP 1dB is measured in the transmitter mode.

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Section: Proposed Integrated Antenna Switchmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

Tokgoz

Kawai

Okada

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Although there are many advantages associated with CMOS technology, such as low cost and high levels of integration, some challenges remain in implementing SPDT switches in this manner. The main challenge is achieving high isolation in the off state, and low insertion loss in the on state, simultaneously [13][14][15]. The π-network has been widely employed at low frequencies, to enhance isolation, through the addition of shunt switches [16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

Park

Lee

et al. 2018

Applied Sciences

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This paper presents two single-pole, double-throw (SPDT) mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS) process. One switch employs cross-biasing (CB) control with a single supply, while the other uses dual-supply biasing (DSB) control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs) in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX) and receiver (RX), as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF) switch is 260 µm × 230 µm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3) of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

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Design of Transmit/Receive Switches in CMOS

Zhang

2012

Wiley Encyclopedia of Electrical and Electronics Engineering

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In this chapter, a concise comparison of wireless communication technologies was provided, from which we noticed that time‐division duplexing ( TDD ) is becoming popular and operating frequency continues increasing. We focused our discussion on an important block, i.e., transmit/receive switch (T/R switch) in a TDD‐based radio front‐end. The discussion started with different categories of T/R switch topologies, followed by device models, and then various design techniques. In particular, we looked at techniques including optimizing device dimensions, maximizing/minimizing substrate resistance, body‐floating, transistor stacking, stepped impedance, and traveling wave concept. Besides a detailed summary on proposed design techniques, recommendation on future work was also provided. Continued innovations and novel ideas on design techniques may provide a comprehensive CMOS solution to the challenges of design of T/R switches for mobile cellular and radio systems operating at 60‐GHz or even high frequencies.

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A Low-Loss 50–70 GHz SPDT Switch in 90 nm CMOS

Cited by 99 publications

References 14 publications

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

Design of Transmit/Receive Switches in CMOS

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