A low noise CMOS frequency synthesizer with dynamic bandwidth control

Abstract

A low noise 0 . 8 p CMOS Phase Locked Loop (PLL) with a maximum output frequency of 120MHz has been developed for a pixel clock generator for a range of computer monitors. Other applications include computer clock generation and disk drives. The synthesizer requires no external components. A low phase noise has been achieved through supply rejection techniques, by placing the oscillator in a high gain feedback loop to minimize its noise contribution, and by dynamically adjusting the PLL bandwidth to maximize the open loop gain.