A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

Abstract

A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,Sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

“…This coincides with the present and the previous numerical analysis results. [13] Therefore, we can see that the drift doping concentration is a very important parameter influencing the electric field peak, and thus determines the breakdown voltage. To verify the proposed breakdown model, the results from the analytical expressions are compared with Medici numerical results.…”

“…For example, to be suited for advanced technology processing, the drift region is formed by a lightly-doped N-well region, so the vertical doping profile is Gaussian. [10][11][12] References [13]- [16] presented a buried P-type layer structure in which the vertical doping profile is discrete, realizing a good trade-off between the breakdown voltage and the on-resistance. In addition, some researchers believed that the vertical linear doping lateral double-diffused metal-oxide-semiconductor (LDMOS) exhibits a superior performance.…”

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

“…[1][2][3][4][5][6][7] One of the main issues when designing LDMOS is the trade-off between breakdown voltage (BV) and specific on-resistance (R on,sp ). [8][9][10][11][12][13][14] Triple reduced surface field (RESURF) technology [15][16][17][18][19][20][21] is an excellent method in mass manufacture to achieve the tradeoff between BV and R on,sp . With a floating p-type buried (P-buried) layer inserted into n-type drift region, the triple RESURF structure provides dual conduction paths to reducing R on,sp .…”

A low specific on-resistance SOI LDMOS with a novel junction field plate

“…[9,10] Furthermore, the trench gate has an extra merit of the isolation for silicon-on-insulator (SOI) LDMOS when the trench gate is extended to the buried oxide layer (BOX). [11] In this paper, a new SOI LDMOS with a novel junction field plate (JFP) and an extended trench gate is presented, which not only breaks through the silicon limit, but also overcomes the drawbacks of the MFP mentioned above. The basic idea of the JFP technique is that a PP-N junction is utilized to form field plate.…”