A Low Operating Voltage ZnO Thin Film Transistor Using a High-κ HfLaO Gate Dielectric

Abstract

This study demonstrates the feasibility of producing a ZnO thin film transistor ͑TFT͒ using hafnium-lanthanum-oxide ͑HfLaO͒ as the gate dielectric. By integrating high-HfLaO with an amorphous ZnO channel, the resulting HfLaO/ZnO TFTs display a low threshold voltage ͑V T ͒ of 0.28 V, a small subthreshold swing ͑SS͒ of 0.26 V/dec, an acceptable mobility ͑ sat ͒ of 3.5 cm 2 /V s, and a good I on /I off ratio of 1 ϫ 10 6 . The SS heavily depends on the HfLaO/ZnO interface charges, a property which is related to the degree of crystallization of ZnO. The low V T and the small SS allow device voltage operation below 2 V for low power application.ZnO-based thin film transistors ͑TFTs͒ 1-14 have been studied extensively in recent years owing to their potential for replacing hydrogenated amorphous or polycrystalline silicon ͑poly-Si͒ TFTs. In addition to the high mobility ͑comparable to that of poly-Si TFTs͒, these ZnO devices do not require prolonged high temperature annealing for dopant activation. This important feature provides faster throughput enhancement and greater energy savings during production. Moreover, ZnO is transparent to visible light and allows low temperature manufacturing; the former advantage especially may assist in the realization of a next generation transparent TFT backplane, 2-6,12-14 and if the high quality of the gate dielectric is also available simultaneously in a low temperature process, the latter advantage may assist in the fabrication of flexible electronics. 15 Although many benefits exist for the ZnO TFT, for further applications involving high speed and low power integrated circuits, the TFTs must possess a low threshold voltage and a small subthreshold swing ͑SS͒.In this article, we have investigated the feasibility of producing a ZnO TFT using a HfLaO gate dielectric 16-20 and an amorphous ZnO ͑a-ZnO͒ channel for low voltage and low power applications. The resulting HfLaO/a-ZnO TFT exhibits a small SS of 0.26 V/dec, a low threshold voltage ͑V T ͒ of 0.28 V, an acceptable mobility ͑ sat ͒ of 3.5 cm 2 /V s, and a good on/off current ratio ͑I on /I off ͒ of 1 ϫ 10 6 at an operation voltage below 2 V. The small V T is due to the unique negative flatband voltage of the La 2 O 3 gate dielectric, 21 where the doping of La 2 O 3 into HfO 2 or the capping of HfO 2 has been widely used to lower the V T of high-Si metal-oxidesemiconductor field-effect transistor. [16][17][18] The small SS is highly related to the crystallized or noncrystallized interface of the ZnO channel with the dielectric, where poorer interface charges are found in crystallized ZnO. Therefore, a trade-off between a higher mobility using crystallized ZnO and lower interface charges in an amorphous material should be satisfied in the ZnO TFTs. ExperimentalThe bottom gate TFT was fabricated on the thick insulating SiO 2 grown on a Si substrate. A 50 nm thick TaN gate electrode was first formed by sputtering and patterning through a shadow mask, and subsequently treated by NH 3 + plasma treatment to improve the TaN/high-interfa...

Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

“…The trap density at/near the gate-dielectric/ ZnO interface can be estimated by equation (3) to be 1.6×10 12 , 1.2×10 12 and 3.6×10 12 cm −2 for the annealing temperature of 200°C, 300°C and 400°C, respectively, indicating that the relatively good electrical performance of the ZnO-TFT with the annealing temperature of 300°C is mainly attributed to the low trap density at/near the gate-dielectric/ZnO interface. In addition, the devices for the three annealing temperatures exhibit a low voltage operation (<8 V), which is close to the results reported using Al 2 O 3 and Ta 2 O 5 gate dielectrics [11,27], but is higher than that of HfLaO and ZrO 2 gate dielectrics [19,20], implying that the electrical performances of the device need to be further optimized for the requirement of low power application in flexible and wearable electronics. Figure 4 exhibits the hysteresis behavior of transfer characteristics under forward and reverse V GS sweeps, and the threshold-voltage shifts (ΔV th =V th·reverse −V th·forward ) of the samples with different NbLaO annealing temperatures are listed in table 1.…”

“…Song et al [18] used Ta 2 O 5 gate dielectric, and mobility over 50 cm 2 V −1 s −1 and low operating voltage of 4 V were achieved in ZnO TFTs fabricated by radio-frequency magnetron sputtering. Su et al [19] fabricated ZnO TFTs with HfLaO gate dielectric, which resulted in a low operating voltage <3 V and a carrier mobility of 3.5 cm 2 V −1 s −1 . Subramanian et al [20] explored solution-processed ZrO 2 gate dielectric and demonstrated a mobility of 20 cm 2 V −1 s −1 and a low operating voltage <3 V in ZnO TFTs.…”

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

“…The capacitors were designed in squares of 300 μm × 300 μm, the capacitances of which measured under AC bias with a frequency of 20 Hz vary from 13 nF cm −2 to 203 nF cm −2 . Due to a high dielectric constant and good insulating property of the amorphous HfLaO x layer, the capacitors maintains a low dissipation factor of ∼3% at 20 Hz. In all ZnO (or ZnSnO) TFTs, the HfLaO x layer ensured an equal interface between the gate insulator and ZnO (or ZnSnO) films.…”

Fabrication and Study on One-Transistor-Capacitor Structure of Nonvolatile Random Access Memory TFT Devices Using Ferroelectric Gated Oxide Film

“…The crystal structure of the various oxide films was improved by the high deposition temperature. However, the oxygen elements in grain boundary of the thin films were broken and lost above the deposition temperatures of 550 o C [41][42][43][44][45][46][47]. To improve the properties of various oxide materials under the post-treatment process, the conventional temperature annealing (CTA) and rapid thermal annealing (RTA) processing were sometimes essential and indispensable technology for crystallization and quality of thin films [48][49][50][51][52].…”