A low-overhead monitoring ring interconnect for MPSoC parameter optimization

Bouajila, Abdelmajid; Lakhtel, Abdallah; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas

doi:10.1109/ddecs.2012.6219023

Cited by 8 publications

(9 citation statements)

References 6 publications

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“…using a dedicated infrastructure [5]- [9]. The works in [7]- [9] stand out as they rely on reusing the existing IEEE 1687 network for monitoring purposes.…”

Section: Introductionmentioning

confidence: 99%

A self-reconfiguring IEEE 1687 network for fault monitoring

Zadegan

Nikolov

Larsson

2016

2016 21th IEEE European Test Symposium (ETS)

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Abstract-Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. In this paper, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected errors are automatically included in the scan path. To enable self-reconfiguration, we propose a modified segment insertion bit (SIB) compliant to IEEE 1687. We provide time analyses on error detection and fault localization for single and multiple faults, and we suggest how the self-reconfiguring IEEE 1687 network should be designed such that time for error detection and fault localization is kept low and deterministic. For validation, we implemented and performed post-layout simulations for one self-reconfiguring network. We show that compared to previous schemes, our proposed network significantly reduces the fault localization time.

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“…using a dedicated infrastructure [5]- [9]. The works in [7]- [9] stand out as they rely on reusing the existing IEEE 1687 network for monitoring purposes.…”

Section: Introductionmentioning

confidence: 99%

A self-reconfiguring IEEE 1687 network for fault monitoring

Zadegan

Nikolov

Larsson

2016

2016 21th IEEE European Test Symposium (ETS)

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“…Bouajila et al [7] use a non-scalable token ring interconnect for transporting sensor data, although the use of this data is unclear. Fattah [8] and Guang et al [1] introduce the conceptual idea of collecting sensor data in individual cores and forwarding them hierarchically to a centralized controller.…”

Section: A Previous Multi-core Sensing Systemsmentioning

confidence: 99%

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

Zhao

Burleson

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Contemporary multi-core architectures deployed in embedded systems are expected to function near the operational limits of temperature, voltage, and device wear-out. To date, most on-chip sensing systems have been designed to collect and use sensor information for these parameters locally. In this paper, a new sensing system to enhance multi-core dependability which supports both the local and global distribution of sensing data in embedded processors is considered. The benefit of the new sensing architecture is verified using the broadcast of microarchitectural parameter signatures which can be used to identify impending voltage droops. Low-latency broadcasts are supported for a range of sensor data transfer rates. Up to a 9% performance improvement for a 16-core system is determined via the use of the distributed voltage droop sensor information (5.4% on average). The entire sensing system, including broadcasting resources, requires about 2.6% of multi-core area.

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“…The communication interface is used to negotiate task migrations in hardware, to provide shared sensor values like workload, and to get updates from the supervisor. All communication between LCTs and the supervisor is transmitted over a dedicated autoring [5] ring-interconnect.…”

Section: Hardware Setupmentioning

confidence: 99%

Sosa

Donyanavard

Mück

Rahmani

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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Resource management strategies for many-core systems dictate the sharing of resources among applications such as power, processing cores, and memory bandwidth in order to achieve system goals. System goals require consideration of both system constraints (e.g., power envelope) and user demands (e.g., response time, energyefficiency). Existing approaches use heuristics, control theory, and machine learning for resource management. They all depend on static system models, requiring a priori knowledge of system dynamics, and are therefore too rigid to adapt to emerging workloads or changing system dynamics. We present SOSA, a cross-layer hardware/software hierarchical resource manager. Low-level controllers optimize knob configurations to meet potentially conflicting objectives (e.g., maximize throughput and minimize energy). SOSA accomplishes this for many-core systems and unpredictable dynamic workloads by using rule-based reinforcement learning to build subsystem models from scratch at runtime. SOSA employs a high-level supervisor to respond to changing system goals due to operating condition, e.g., switch from maximizing performance to minimizing power due to a thermal event. SOSA's supervisor translates the system goal into lowlevel objectives (e.g., core instructions-per-second (IPS)) in order to control subsystems by coordinating numerous knobs (e.g., core operating frequency, task distribution) towards achieving the goal. The software supervisor allows for flexibility, while the hardware learners allow quick and efficient optimization. We evaluate a simulation-based implementation of SOSA and demonstrate SOSA's ability to manage multiple interacting resources in the presence of conflicting objectives, its efficiency in configuring

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A low-overhead monitoring ring interconnect for MPSoC parameter optimization

Cited by 8 publications

References 6 publications

A self-reconfiguring IEEE 1687 network for fault monitoring

A self-reconfiguring IEEE 1687 network for fault monitoring

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors

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