A low-overhead PUF based on parallel scan design

Wang, Wenxuan; Cui, Aijiao; Qu, Gang; Li, Huawei

doi:10.1109/aspdac.2018.8297406

Cited by 11 publications

(2 citation statements)

References 21 publications

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“…It can be seen that a SR-latch with NAND gates can be used as an arbiter to detect the speed of signal transmission. We also name this SR-latch as NAND-type arbiter (referred to as PA), similarly, an arbiter of SR-latch with NOR gates is called NOR-type arbiter (referred as NA) [48].…”

Section: Architecture Of Proposed Scan Methodsmentioning

confidence: 99%

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Wang¹,

Gong²,

Wang³

et al. 2023

Computers, Materials &Amp; Continua

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The advanced integrated circuits have been widely used in various situations including the Internet of Things, wireless communication, etc. But its manufacturing process exists unreliability, so cryptographic chips must be rigorously tested. Due to scan testing provides high test coverage, it is applied to the testing of cryptographic integrated circuits. However, while providing good controllability and observability, it also provides attackers with a backdoor to steal keys. In the text, a novel protection scheme is put forward to resist scan-based attacks, in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuseantifuse structures in a non-linear shift register (NLSR), then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells. If the key is right, the chip can be tested normally; otherwise, the data in the scan chain cannot be propagated normally, it is also impossible for illegal users to derive the desired scan data. The proposed technique not only enhances the security of cryptographic chips, but also incurs acceptable overhead.

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Section: Architecture Of Proposed Scan Methodsmentioning

confidence: 99%

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Wang¹,

Gong²,

Wang³

et al. 2023

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

“…Various types of PUF have been developed, though detailed analyses of stability and reliability are substantially lacking. Among others, PUF can be classified as follows: memory-based PUF; PUF based on delay [4]; and physical PUF. However, the grouping of the PUFs is not finalized, as researchers are continuously looking for new and better PUF models.…”

Section: Introductionmentioning

confidence: 99%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

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A dependable and resource-frugal ring oscillator physically unclonable function

Hossain,

Tabassum

et al. 2024

International Journal of Electronics

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A low-overhead PUF based on parallel scan design

Cited by 11 publications

References 21 publications

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

A dependable and resource-frugal ring oscillator physically unclonable function

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