A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process

Lin, J.

doi:10.1109/jssc.2005.856580

Cited by 47 publications

(13 citation statements)

References 12 publications

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“…This is consistent with Equation 2. The nonlinearity of the DCO gain can be reduced if desired by tapering up the capacitor values of a thermometer-encoded capacitor array [11].…”

Section: Experiments Resultsmentioning

confidence: 99%

“…We use thermometer coding for the digital control word D i , i ∈ {1,2,... 2n} and physically place two unit capacitors in close locations when their index numbers are close to each other to reduce the nonlinearity caused by process variation [11]. We alternately index the unit capacitors between the two banks to further improve resolution.…”

Section: The Proposed Fbar-based Oscillatormentioning

confidence: 99%

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A wide-tuning digitally controlled FBAR-based oscillator for frequency synthesis

Parkery

Ruby

et al. 2010

2010 IEEE International Frequency Control Symposium

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This paper presents a wide-tuning digitally controlled FBAR-based oscillator in a 0.18µm CMOS process. The oscillator is tuned with a digitally-switched capacitor array to achieve a tuning range of >7000ppm, an over eightfold improvement over previously published low power FBARbased VCOs. The high Q FBAR allows frequency tuning to be implemented with a switched-capacitor array with relatively large unit capacitors to achieve a sufficiently fine resolution for frequency synthesis. Our oscillator achieves a measured phase noise of -99dBc/Hz and -142dBc/Hz at 10kHz and 1MHz offsets respectively at a carrier frequency of 1.50GHz while consuming less than 4mW.

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“…This is consistent with Equation 2. The nonlinearity of the DCO gain can be reduced if desired by tapering up the capacitor values of a thermometer-encoded capacitor array [11].…”

Section: Experiments Resultsmentioning

confidence: 99%

Section: The Proposed Fbar-based Oscillatormentioning

confidence: 99%

A wide-tuning digitally controlled FBAR-based oscillator for frequency synthesis

Parkery

Ruby

et al. 2010

2010 IEEE International Frequency Control Symposium

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“…XO close-in phase noise is dominated by the up-converted flicker noise of core driver transistor, biasing circuit and the first stage clock buffer [7]. Therefore, large size core driver transistor and clock buffer have to be utilized to reduce their flicker noise contribution.…”

Section: Low Noise Crystal Oscillatormentioning

confidence: 99%

Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS

Qin

Zhou

et al. 2014

IEICE Electron. Express

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This paper describes several phase noise suppression techniques for X-band (8-12 GHz) frequency synthesizer design in 65 nm CMOS technologies. A low noise voltage generator for varactor DC biasing is proposed to minimize its contribution to VCO phase noise, which minimizes the outof-band phase noise. A crystal oscillator with low noise biasing is proposed to prevent bias and supply noise from deteriorating its output phase noise, which improves the in-band phase noise. A frequency synthesizer prototype was implemented in 65 nm CMOS technology and generates 8.6-12.4 GHz output frequencies, with a measured phase noise performance of −90 dBc/Hz and −110 dBc/Hz at 10-kHz (in-band) and 1-MHz (out-of-band) frequency offset, respectively. The prototype draws 33 mA current from a 1.2 V power supply and the core circuit area is 0.2 mm 2 . The performance comparison demonstrates the prototype achieves the best phase noise performance among all published frequency synthesizers in X-band or higher frequencies.

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“…The carrier frequency of the DCO is tuned with coarse, medium, and fine-tuning capacitor banks , , and while the frequency deviation constant is set using . Each capacitor bank is thermometer coded and predistorted as in [12] to improve linearity in digital-to-frequency conversion and guarantee monotonicity for each bank. This is critical since the DCO will be placed in a FCL and non-monotonicity could result in instability.…”

Section: Capacitor Array With Predistortionmentioning

confidence: 99%

A 350 $\mu$W CMOS MSK Transmitter and 400 $\mu$W OOK Super-Regenerative Receiver for Medical Implant Communications

Bohorquez

Chandrakasan

Dawson

2009

IEEE J. Solid-State Circuits

213

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Recent advances in the medical field are spurring the need for ultra-low power transceivers for wireless communication with medical implants. To deal with the growing demand for medical telemetry, the FCC commissioned the Medical Implant Communications Services (MICS) standard in 1999 in the 402-405 MHz band. This paper presents a 350 W FSK/MSK direct modulation transmitter and a 400 W OOK super-regenerative receiver (SRR) specifically optimized for medical implant communications. The transceiver is implemented in 90 nm CMOS and digitally tunes 24 MHz in frequency steps smaller than 2 kHz. The transmitter meets MICS mask specifications with data rates up to 120 kb/s consuming only 2.9 nJ/bit; the receiver has a sensitivity better than 99 dBm with a data rate of 40 kb/s or 93 dBm with a data rate of 120 kb/s consuming 3.3 nJ/bit. A frequency correction loop incorporating the base-station is prototyped to eliminate the need for a frequency synthesizer in the implant while still achieving frequency stability of less than 3 ppm.

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A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process

Cited by 47 publications

References 12 publications

A wide-tuning digitally controlled FBAR-based oscillator for frequency synthesis

A wide-tuning digitally controlled FBAR-based oscillator for frequency synthesis

Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS

A 350 $\mu$W CMOS MSK Transmitter and 400 $\mu$W OOK Super-Regenerative Receiver for Medical Implant Communications

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