A low-phase-noise 0.004ppm/step DCXO with guaranteed monotonicity in 90nm CMOS

Abstract

Texas Instruments, Dallas, TXGSM and WCDMA standards require 0.1ppm frequency accuracy. This is achieved through the AFC loop in the digital baseband (DBB) that adjusts the frequency of the crystal oscillator based on the demodulated/decoded reference signals from the basestation. The popular implementation, which uses an expensive external VCXO and provides the analog control voltage from the AFC DAC, is not cost and implementation effective. A DCXO, therefore, provides an attractive alternative as it requires only an inexpensive external crystal and the controlled signal can be digitally derived from the DBB. The keys for a successful DCXO design are low phase noise, sub-0.1ppm of tuning step, and a wide monotonic tuning range to cover the crystal variations. Such a design is presented in this paper. Implemented in 90nm CMOS, it occupies 0.18mm 2 and achieves phase noise of -140dBc/Hz @1kHz and -152dBc/Hz @10kHz offset from 26MHz, guaranteed monotonicity of ~0.004ppm/step across the entire 70ppm tuning range, and 0.5ppm/V of supply voltage pushing which relaxes the supply noise and accuracy requirement. Figure 22.5.1 is the simplified schematic of this DCXO. It includes a current source, a DCXO core with a 14b AFC frequency-tuning capacitor DAC, a digital oscillation amplitude control loop (digital portion not shown), and an output buffer. To minimize pin count, a Colpitts-style oscillator is chosen, requiring just one crystal pin besides VDD and GND. The main oscillator core, including PMOS MP1, a fixed value feedback MIM capacitor C MIM , and a 14b tunable accumulation MOS capacitor DAC, provides the frequency tuning and the negative resistance to compensate for the crystal loss. A PMOS device is used in the main oscillator core to reduce the substrate noise coupling. An accumulation mode MOS capacitor, instead of an MIM capacitor, is used in the 14b DAC for area saving. The 0.5ppm/V of low supply pushing is achieved by the combination of an active impedance boost circuit (A1, MN1 and MN2) in the Widlar current source and the active cascode (A2 and MP2) in the oscillator core. Both effectively reduce the oscillator current dependency on VDD. The output buffer, which converts the 26MHz sine wave oscillation to the rail-to-rail square wave, is just a cascade of 3 inverters. The common-mode voltage of the oscillation is set to the logic threshold voltage of the first inverter by a scaled-down replica inverter; good phase noise and good duty cycle are therefore achieved. The oscillation amplitude control loop is done in a digital fashion for better phase noise performance. It comprises a peak detector, a 4b flash ADC, and an 8b current DAC to sense and regulate the oscillation amplitude digitally. During a burst transmission or reception, the amplitude control loop is disabled to prevent the excessive noise contribution from the loop. Figure 22.5.2 shows the detailed schematic of the 14b capacitor DAC. The top 10 MSBs are made of a 32 × 32 thermometer coded capacitor array. An appropriate combination of row and c...