A Low Phase Noise <i>K</i>-Band VCO With a Threshold Voltage-Based Current Source

Huang, Jian; Sun, Bing; Li, Jinwei; Wu, Lei; Chang, Hudong; Jia, Rui; Liu, Honggang

doi:10.1109/lmwc.2022.3162309

Cited by 4 publications

(1 citation statement)

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“…The R

_{1}

, M

_{1}

, and M

_{2}

generate the reference current. We can calculate the current as 13

I_{1} = \frac{\sqrt{4 β R_{1} V_{t h} + 1} + 2 β R_{1} V_{t h} + 1}{2 β R_{1}^{2}} .

…”

Section: Main Circuits Designmentioning

confidence: 99%

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

Sun

Huang

et al. 2023

Circuit Theory & Apps

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This paper presents a wide‐band charge‐pump phase‐locked loop (CPPLL) with reference spur reduction techniques. To broaden the frequency range without deteriorating phase noise, a 6‐bit capacitor array‐based VCO and an automatic frequency calibrator (AFC) are used. A compact loop filter technique saves the capacitor area and maintains the bandwidth. Also, a novel charge pump with dynamic current matching circuit is proposed to reduce the reference spur of the PLL. The current mismatch is less than 0.22 normalμA (0.16%) over the voltage range from 0.75 to 1.55 V. Fabricated in 0.13 normalμm CMOS technology, the proposed PLL achieves a locking range of 7.6–12.3 GHz (47.2%), with a 25 MHz frequency interval. The PLL consumes 23.3 mA from a 2.5 V supply voltage and occupies a core area of 0.92 mm × 0.72 mm. The reference spur of the proposed PLL is measured to be −81.1 dBc, and in‐band phase noise reaches −110.8 dBc/Hz at 1 MHz offset frequency from the 9.5 GHz carrier frequency.

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“…The R