A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

Murphy, David; Gu, Qun Jane; Wu, Yuexin; Jian, Heng-Yu; Xu, Zhiwei; Tang, Adrian; Wang, F.; Chang, Mau-Chung Frank

doi:10.1109/jssc.2011.2143950

Cited by 83 publications

(44 citation statements)

References 16 publications

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“…This range covers operation over 22. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. 4 GHz, with margin, meeting requirements for a 60-GHz superheterodyne radio [2].…”

mentioning

confidence: 99%

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

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mentioning

confidence: 99%

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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“…Generally, the output phase noise of a PLL frequency synthesizer is mainly determined by the VCO phase noise and the phase noise of the reference signal source [6,7]. Because the L VCO (f) is much higher than the L REF (f), so the latter to the total phase noise contribution of the PLL4 can be neglected.…”

Section: A Phase Noise Estimatementioning

confidence: 99%

Design of a Full-Coherent Millimeter Wave Radar Frequency Synthesizer

Chen¹,

Xu²,

Peng³

2017

Proceedings of the 3rd International Conference on Wireless Communication and Sensor Networks (WCSN 2016)

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Abstract-In this paper, with the combination of DDS, PLL, multiplier and mixing techniques, a millimeter wave (mm-wave) full-coherent frequency synthesizer with low phase-noise and spurs is developed. It includes a mm-wave source. A linear frequency modulation (LFM) generator and a microwave source serving as the second local oscillator for the receiver. An external 100 MHz temperature-controlled crystal oscillator is used as the coherent clock for all the sources. The phase noise and spurs of the mm-wave signal have been analyzed and estimated. Measured results show that the output frequency is 34.855~34.865 GHz, the stepping frequency is 100 KHz, the output power is larger than 16 dBm, and the phase noise level is about -92 dBc/Hz at an offset of 10 KHz.

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“…이중에서 직접 변환 방식 [1]～ [3] 은 DC 오프셋, I/Q 부정합, LO 피드스루(feed-through)와 같은 단점들이 존재한다. 따라서 그러한 문제점들을 회피함과 동시에, 상대적으로 낮은 출력 주파수와 작은 K VCO 로 설계할 수 있는 슬라이딩-IF 구조 [4]～ [6] 가 더욱 선호된다. [5], [8] .…”

Section: ⅰ 서 론unclassified

“…이는 전압 제어 발 진기에 대해 높은 커패시터 부하를 야기하므로 전압 제 어 발진기의 출력 주파수 변화범위가 제한되는 문제가 발생하며, 또한 추가적으로 바이어스 전압을 공급해야 하 는 문제가 있다. 이러한 이유들로 인하여 그림 3(b)와 같 이 전압 제어 발진기와 ILFD 사이에 버퍼를 위치시키고, 전압 제어 발진기의 출력을 버퍼를 거쳐 ILFD 입력 단에 주입하는 방법이 선호된다 [6], [8], [10] 버퍼는 전압 제어 발진 기와 ILFD 상호간에 발생할 수 있는 간섭을 차단할 수 있 그림 2. 제안된 40-GHz PLL 구조 [12], [13] .…”

Section: ⅰ 서 론unclassified

Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider

Nam¹,

Sohn²,

Shin³

2016

The Journal of Korean Institute of Electromagnetic Engineering

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This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and lowpower consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

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A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

Cited by 83 publications

References 16 publications

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Design of a Full-Coherent Millimeter Wave Radar Frequency Synthesizer

Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider

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