A low-power 2nd-order CT delta–sigma modulator with an asynchronous SAR quantizer

Abstract

This paper presents a low voltage continuoustime delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 lW from a 800 mV power supply.

A Low Power Sigma-Delta Modulator with Hybrid Architecture

“…In order to realize a low power consumption circuit, there are many existing structures and schemes for a Σ-Δ modulator module such as [ 18 ], where a Σ-Δ modulator based on the SAR quantization structure is reported. It adopts a second-order integrator with a 4-bit quantizer architecture and conducts post-simulation on the circuit behavior, the circuit itself and at the layout level, which verifies the feasibility of the scheme.…”

“…If other device losses and power losses are not considered, the actual power consumption of the chip is less than 2.5 mW. Reference [ 18 ] adopts a second-order 4-bit quantizer structure which has a simulated power consumption of 69 μW and lower than the proposed architecture. However, it adopts a 65 nm process and the simulated data does not consider the power and circuit loss, so it cannot be compared at the same level.…”

Efficient CTDSM based on GM‐C quantiser and improved dynamic element matching

“…Here, a decoder is used to convert the binary code to thermometer code 2 B − 1 and the origin of thermometer code is moved to the new location using a logarithmic shifter. Mathematically, DAC mismatch noise Noise DAC can be expressed as [19] Noise DAC = 1 − z −1 × IM ptr z (5) where the first-order high-pass filter (HPF) of the created integral mismatching error is represented using (6) where mean of the DAC unit components is represented as D avg , D j represents the jth DAC component value and e j represents DAC mismatch error of jth DAC component. Since, the tonal behaviour of the traditional DWA contains a limitation for certain periodic inputs, it creates the DAC mismatching error as a first-order HPF.…”

“…where β¯H and β¯L represent the mean of mismatching error of upper half and lower half DAC, respectively. The first two terms can be derived using (6) and the third term represents the linearity of an additional gain error with the DAC input. A non-linear error based on the shape of W(n) created using a required HPF and the difference of the average gain of 2 half DACs is represented in the fourth term.…”

“…The power and area of CTDSMs can be saved with the help of digital modulation methods and noise shaping SAR (NSSAR) quantisers. However, the sampling frequency is limited by those circuits because they present more logic delays [6].…”