A low-power 3-phase half rail pass-gate differential logic

A generalized algorithm with efficient architectures for high-speed parallel scramblers with reduced registers is proposed. The algorithm can be applied to any scrambler polynomials with three terms to achieve small numbers of registers and fan-outs. The critical paths only have one register and one XOR gate, which are merged into a dynamic differential circuit for implementation. The results show that more than 50% chip area can be reduced in comparison with literatures, and the power dissipation is only 3.7mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps, using TSMC 0.18 μm CMOS technology.

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A low-power 3-phase half rail pass-gate differential logic

Cited by 3 publications

References 7 publications

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