A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip

Abstract

This brief presents a four-level pulse-amplitude modulation (4-PAM) transceiver for latency-sensitive network-on-chip (NoC) applications. The proposed source-synchronous PAM transceiver uses a novel encoder/decoder and dual-sampling technique that transmits and receives two data streams through a shared single-ended channel simultaneously. A conventional PAM transceiver for heterogeneous NoCs is sensitive to a possible latency skew between on-chip intellectual properties during encoding/decoding multiple PAM signals. To mitigate this problem, a dual-sampling technique that makes the link insensitive to PAM latency skews is used to transfer data signals reliably. The proposed 4-PAM transceiver is designed and fabricated using the 130-nm CMOS technology at a 1.2-V supply. The proposed transceiver operates at 6 Gb/s/pin with a power efficiency of 0.7 pJ/b/pin and with a 0.13-mm 2 die area. The proposed transceiver achieves a bit error rate of < 10 −10 , with 2 7 -1 and 2 15 -1 pseudorandom binary sequences at 6 Gb/s/pin. Index Terms-Complementary metal-oxide-semiconductor (CMOS), double sampling, network-on-chip (NoC), pulseamplitude modulation (PAM), transceiver.

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