A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications

Damghanian, Masumeh; Azhari, Seyed Javad

doi:10.1016/j.vlsi.2017.01.006

Cited by 9 publications

(4 citation statements)

References 20 publications

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Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

“…A flash ADC is presented to improve chip area and performance speed with high resolution by employing multi segment encoder with MOS current mode logic (MCML) in the article [22]. In this article the novel structure maintains the simplicity of the encoder structure by using two segment encoders and a smaller number of multiplexers [22]. Another discussion on case study of pipelined ADC presented in the same year in which a vigorous calibration technique of multivalued ADC using the integral INL based calibration is obtained [23].…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

See 1 more Smart Citation

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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“…Several encoders [7][8][9][10][11][12][13] are described in the literature, in which Fat-Tree encoder [14] exhibits better results as compared to others. For the design of encoders, complementary logic (CML) [15] based gates are efficient in terms of noise but power consumption is more due to extra biasing circuits. Pseudo-NMOS based encoder [10] is fast but has a large PMOS load which increases with the increase in number of inputs.…”

Section: Introductionmentioning

confidence: 99%

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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“…However, ADC (SAR) is slightly unfit for the applications which require very high speed with high resolution [12], [13]. The count of significant components like comparators, encoders/decoders, pre-amplifiers, registers increases exponentially as the designers go for higher resolution and fast speed [14], [15].…”

Section: Introductionmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Khatak

Kumar

Dhull

2020

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The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.

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A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications

Cited by 9 publications

References 20 publications

Analog to Digital Converters (ADC): A Literature Review

Analog to Digital Converters (ADC): A Literature Review

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

International Journal of Electronics and Telecommunications

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