A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

Yan, Na; Ma, Lei; Xu, Yongxin; Chen, Sizheng; Liu, Xusong; Xiang, Junhui; Min, Hao

doi:10.1109/access.2018.2890073

Cited by 15 publications

(5 citation statements)

References 16 publications

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“…It is observed from Table 4 that the proposed ADPLL has fast locking time as compared to designs in previous papers. 17,23,24 There is a reduction of 45% in the locking time and 11% reduction in the power consumption with expense of only 7% increase in the jitter as compared to architecture reported in Sahani et al 17 The proposed ADPLL has better jitter and power consumption as compared to work presented in the Tao and Heng. 22 The locking time is 1.7 μs of proposed ADPLL after postlayout simulations.…”

Section: Discussionmentioning

confidence: 85%

“…The PVT variation in periodic jitter without calibration for ADPLL is shown in Figure 7. The total variation of 22.9% is 17 Tao and Heng 22 ur Rahman et al 23 Yan et al 24 De Caro et al 25 Sahani et al 26 Supply voltage (V) observed in the ADPLL without calibration. The proposed 3-bit flash TDC with resolution of 3 ps and periodic jitter of 0.46 ps is used.…”

Section: Adpll Simulation Resultsmentioning

confidence: 99%

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A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

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Section: Discussionmentioning

confidence: 85%

Section: Adpll Simulation Resultsmentioning

confidence: 99%

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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“…However, in such applications, the battery's lifetime is limited [14]. The key specification for the frequency range is the faster lock-in time [15].…”

Section: Introductionmentioning

confidence: 99%

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

Velamarthi Spandana,

2023

IJRITCC

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All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly. Therefore, proposed a novel particle swarm based ADPLL (PS-ADPLL) with Coordinate Rotation Digital Computer (CORDIC) algorithm to attain the lock state of the ADPLL for the low-frequency applications. In the proposed architecture, the D flip-flop matches the frequency and the phase of the output and reference pulses and produces an error signals up and down signal. The up/down counter removes the higher frequency part and produces a carry and the borrow signal. These carry and borrow signals are then fed into the increment decrement counters to produce the output signal matching the frequency of the reference signal. However, the time delay is increased for low-frequency applications, which is critical for the lock state. So, the delay line length is calculated by the CORDIC algorithm and is optimized by the particle swarm activated in the phase detector to match the output pulse with the reference pulse and make ADPLL into a locked state. The presented PS-ADPLL is tested in FPGA. Furthermore, the performance parameters are evaluated and compared with other current techniques to calculate the improvement score.

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“…In many applications such as all-digital phase-locked loops (ADPLLs) [1], chemical sensors readout [2], frequency synthesizers [3][4][5][6], and time-of-flight (ToF) systems [7], time-to-digital converters (TDCs) play an important role by measuring a time interval. Thus far, many TDCs have been presented which have been trying to show high signal-to-noise ratio (SNR), resolution, bandwidth, and linearity.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

et al. 2019

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An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved.

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A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

Cited by 15 publications

References 16 publications

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

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