A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Kumar, Mithilesh; Majumder, Alak; Mondal, Abir J.; Raychowdhury, Arijit; Bhattacharyya, Biswajit

doi:10.1016/j.vlsi.2022.08.008

Integration

2022

DOI: 10.1016/j.vlsi.2022.08.008

|View full text |Cite

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Mithilesh Kumar

Alak Majumder

Abir J. Mondal

et al.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2024

Publication Types

Select...

Article1

Relationship

Self Cite0

Independent1

Authors

Journals

Cited by 1 publication

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Design of Variation Tolerant Near Threshold Processor Using Artificial Ecosystem Optimizer with Hybrid Deep Learning

Gundaala,

2024

JMC

View full text Add to dashboard Cite

Recently, several applications of data mining and pattern recognition require statistical signal processing (SP) to be used and machine learning (ML) techniques for processing massive data volumes in energy-constrained contexts. It is developing interest in executing difficult ML techniques like convolutional neural network (CNN) on lesser power embedding environments to allow on-device learning and inference. Several of these platforms are that utilized as lower power sensor nodes with lower to medium throughput conditions. Near threshold processor (NT) proposals are appropriate for these applications where as affected by a vital enhancement in variants. This research offers an Artificial Ecosystem Optimizer with Hybrid Deep Learning for Variation-Tolerant Near-Threshold Processor (AEOHDL-VTNT). The inference of embedded systems at the network edge serves as the foundation for the AEOHDL-VTNT approach that is being discussed. In the described AEOHDL-VTNT approach involves two primary processes: HDL-based VTNT design and hyper parameter tweaking. Initially, the HDL model is used to develop the VTNT. Next, in the second step, the AEO method is used for hyper parameter tweaking of the HDL model, which improves the HDL's overall performance. A number of simulations were carried out to show how the AEOHDL-VTNT approach improved performance. The simulation results showed that the AEOHDL-VTNT approach outperformed other models.

show abstract

Design of Variation Tolerant Near Threshold Processor Using Artificial Ecosystem Optimizer with Hybrid Deep Learning

Gundaala,

2024

JMC

View full text Add to dashboard Cite

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Cited by 1 publication

References 10 publications

Design of Variation Tolerant Near Threshold Processor Using Artificial Ecosystem Optimizer with Hybrid Deep Learning

Design of Variation Tolerant Near Threshold Processor Using Artificial Ecosystem Optimizer with Hybrid Deep Learning

Contact Info

Product

Resources

About