A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique

Garghetti, Alessandro; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/iscas.2018.8350910

Cited by 4 publications

(1 citation statement)

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“…The results, confirmed by circuit simulations, inspire a new divider topology (Sect. III), where a pMOS tail transistor M 4 is used as an extra divide-by-two injection path [6]. A thorough comparison between the performance of conventional and novel divide-by-three ILFD topologies in 65-nm CMOS is provided in Sect.…”

Section: Introductionmentioning

confidence: 99%

A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking

Garghetti

Lacaita

Levantino

2019

IEEE Trans. Circuits Syst. I

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The paper presents a comprehensive analysis of signal intermixing taking place across the injectors of frequencydivide-by-three circuits with divide-by-two secondary locking. The analytical results confirmed by circuit simulations provide an insightful understanding of the circuit operation, and inspire the design of a novel single-inductor injection-locked frequency divider (ILFD) by three, where injection is reinforced by a dual-injection scheme with no penalty in power dissipation. The novel circuit, when benchmarked against existing ILFD topologies, optimized in a 65-nm LP CMOS process, shows about a three-time larger locking range with respect to the single-inductor divider by three with a floating-source injector, and about a 40% improvement with respect to the single-inductor divider by three with divide-by-two locking, for the same power dissipation. The novel topology has been adopted in a 15-GHz divider by three for a 5G radio-frequency synthesizer, reaching a 23.6% locking range at 1.56-mW dc power, featuring one of the best performances among divide-by-three ILFDs and a compact size of only 0.09 mm 2 .

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Section: Introductionmentioning

confidence: 99%