2014
DOI: 10.1007/s11432-014-5226-1
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A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

Abstract: A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667/800/1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG). To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A splitcon… Show more

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Cited by 5 publications
(1 citation statement)
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“…With the advantages of high stability [1][2][3] and strong portability [4][5][6][7], the all digital delay-locked loop (ADDLL) is widely used as multiphase clock generator [8][9][10][11] in double data rate (DDR) synchronous interfaces. The Open NAND Flash Interface Specification (ONFI) [12], which is the industry standard, strictly stipulates the timing requirements of non-volatile double data rate (NV-DDR) high-speed interfaces.…”
Section: Introductionmentioning
confidence: 99%
“…With the advantages of high stability [1][2][3] and strong portability [4][5][6][7], the all digital delay-locked loop (ADDLL) is widely used as multiphase clock generator [8][9][10][11] in double data rate (DDR) synchronous interfaces. The Open NAND Flash Interface Specification (ONFI) [12], which is the industry standard, strictly stipulates the timing requirements of non-volatile double data rate (NV-DDR) high-speed interfaces.…”
Section: Introductionmentioning
confidence: 99%