A low-power carry skip adder with fast saturation

Schulte, M.J.; Chirca, K.; Glossner, J.; Wang, Haoran; Mamidi, S.; Balzola, P.; Vassiliadis, S.

doi:10.1109/asap.2004.1342477

Cited by 7 publications

(4 citation statements)

References 13 publications

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“…For the matcher ripple logic, (7) Most theorems developed to accelerate the carry chain in adders can be applied to the matcher circuit. In order to improve its performance, carry-look-ahead, block-carrylook-ahead and the combination of carry-skip and carrylook-ahead, carry-select and carry-look-ahead techniques have been applied and analysed.…”

Section: Matcher Architecturementioning

confidence: 99%

See 1 more Smart Citation

Design and analysis of matching circuit architectures for a closest match lookup

McLaughlin¹,

Kupzog²,

Blume³

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.

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Section: Matcher Architecturementioning

confidence: 99%

“…An optimised skip structure is proposed [7] using a look-ahead technique within the skip blocks using variable block sizes. This approach can be transferred to the matcher problem.…”

Section: Skip and Look-ahead Approachmentioning

confidence: 99%

Design and analysis of matching circuit architectures for a closest match lookup

McLaughlin¹,

Kupzog²,

Blume³

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

View full text Add to dashboard Cite

show abstract

“…the ripple output (7) Most theorems developed to accelerate the carry chain in adders can be applied to the matcher circuit. In order to improve its performance, carry-look-ahead, block-carrylook-ahead and the combination of carry-skip and carrylook-ahead, carry-select and carry-look-ahead techniques have been applied and analysed.…”

Section: Matcher Architecturementioning

confidence: 99%

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup

Kupzog¹,

Blume²,

Noll³

et al. 2006

Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services (AICT-ICIW'0

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“…Carry look-ahead adder (CLA) [2] has the smallest delay, but the more area share. Carry-skip adder (CSA) [3] is a optimize method between CRA and CLA. Conditional Carry Select (CCS) [4] [5] and Conditional Sum Select (CSS) [6] reduce the delay by some parallel circuit to carry-chain.…”

Section: Introductionmentioning

confidence: 99%

The Research of Large Numbers Adder to Rapid Realization Method

Fang

Tinggang²,

Han³

et al. 2008

2008 IEEE Pacific-Asia Workshop on Computational Intelligence and Industrial Application

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This paper has presented a method of carry forecast between groups to improve the speed of the large numbers adder in some cryptography and other applications. Firstly, the large numbers is divided into many groups, in which the delay of carry-chain is reduced by Carry look-ahead; second, the group addition operation is finished by carry forecast between groups; lastly, the addition sum of different carry forecast state was selected as the final result basing on the carry state. The delay of the large numbers addition which data width is more than 1024-bit is constantly 19 gate levels. Because of the carry transferring is translated into the carry state equation comparison, the carry delay of adder is not changing with the increasing of data width.

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A low-power carry skip adder with fast saturation

Cited by 7 publications

References 13 publications

Design and analysis of matching circuit architectures for a closest match lookup

Design and analysis of matching circuit architectures for a closest match lookup

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup

The Research of Large Numbers Adder to Rapid Realization Method

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