A low-power circuit technique for domino CMOS logic

“…Domino CMOS [14][15][16] logic techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics when compared with the standard fully complementary static CMOS logic. 17,18 However, the major drawback of the domino dynamic logic is its excessive power dissipation due to switching activity and clock load.…”

Section: Previous Workmentioning

confidence: 99%

Dual Threshold Voltage Domino Adder Design With Pass Transistor Logic Using Standby Switch for Reducing Sub-Threshold Leakage Current

Yuan

2014

J CIRCUIT SYST COMP

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Standby switch can strongly turn o® all the high threshold voltage transistors, which enhances the e®ectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without a®ecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit con¯guration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 m CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25 C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry lookahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

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