A Low-Power Design for an Elliptic Curve Digital Signature Chip

Abstract

We present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function offered by our hardware design is Elliptic Curve Optimal El Gamal digital signature generation. Our parameters are defined over the finite field GF (2 178), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures. Our optimizations include using the point-halving algorithm for elliptic curves, field towers to speed up the finite field arithmetic in general, and further enhancements of basic finite field arithmetic operations. The result is a synthesized VHDL digital signature design (using a CMOS 0.5µm, 5V , 25 • C library) of 191,000 gates that generates a signature in 4.4 ms at 20 MHz.

Low-Complexity Bit-Parallel Square Root Computation over GF(2^{m}) for All Trinomials

“…Let us reduce this vector using rule (4). Hence, the upper half of A 2 (i.e., the m most significant bits) in Eq.…”

“…Arithmetic over binary extension fields GF (2 m ) has many important applications, particularly in the theory of error control coding, symmetric block ciphers and elliptic curve cryptosystems [1,2,3,4,5]. Those applications typically require high performance implementation of most if not all of the basic finite field operations such as field addition, subtraction, multiplication, division, exponentiation and square root [6].…”

“…In particular, field square root computation has become an important building block in the design of some elliptic curve primitives such as point compression and point halving [1,3,4]. Moreover, recently, a novel parallel formulation of the standard Itoh-Tsujii multiplicative inverse algorithm for multiplicative inverse computation over GF (2 m ) using as main building blocks field multiplication, field squaring and field square root operators was proposed in [7].…”

A Low-Cost ECC Coprocessor for Smartcards

“…ISE are not useful for 8-bit platforms because slow data transport in 8-bit systems will deteriorate accelerated field operations. Alternatives are heavy-weight accelerators for complete EC operations [4,5,7,8] or hardware-software co-design approaches where com-putational intensive tasks are done by an EC coprocessor [9]. These coprocessors can either calculate all finite field operations [12] or support only multiplication as the most demanding finite field operation [10,11].…”

“…Therefore, they often have hardware support for calculating the modular inverse using the extended Euclidean algorithm. An example is the so-called Domain-Specific Reconfigurable Cryptographic Processor by J. Goodman et al [4] and the GF(2 178 )-EC-processor by R. Schroeppel et al [5]. The latter can calculate inverses only in GF (2 178 ).…”