A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays

Wu, Dong; Gao, Cencen; Liu, Hui; Xie, Ning

doi:10.1109/tcsi.2014.2341117

Cited by 13 publications

(3 citation statements)

References 25 publications

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“…Speed of a discrete-time delta-sigma ADC is mostly limited by the settling time of an integrator that dominates the whole power consumption, and effectively doubled settling time of integrators is allowed in the double sampling scheme. Therefore, a double sampling delta-sigma ADC is often used in sensor applications where high-resolution and low power consumption are critical [ 19 , 20 ]. The proposed double sampling Hall sensor system and its operation timing diagram are shown in Figure 7 .…”

Section: Proposed Hall Sensor Architecturementioning

confidence: 99%

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

Lee

et al. 2020

Sensors

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A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm2, and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

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Section: Proposed Hall Sensor Architecturementioning

confidence: 99%

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

Lee

et al. 2020

Sensors

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“…To meet those requirements, a two-step operation of coarse and fine conversion is adopted like an extended counting ADCs [18]- [20]. The extended counting ADCs perform the coarse conversion with the incremental ADC and the fine conversion with the Nyquist ADC.…”

Section: A Basic Concept Of Two-step Operationmentioning

confidence: 99%

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Hong

Kwon

2015

IEEE Trans. Circuits Syst. I

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This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 CMOS image sensor process with a pixel array that has an image format of 648 488 and a pixel size of . The measured results show a random noise of 108 , a dynamic range of 60.9 dB, a differential nonlinearity of 1.02/ 0.34 least significant bit (LSB), and an integral nonlinearity of 0.64/ 0.54 LSB.Index Terms-Column-parallel readout, incremental analog-todigital converter (ADC), successive approximation.

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“…Many class AB topologies have been reported [1][2][3][4][5][6][7] that have I out-MAX > 2I bias . One of the figures of merit used frequently to compare class AB OTAs is the output current enhancement factor CE = I out-MAX /2I bias .…”

Section: Introductionmentioning

confidence: 99%

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

Pourashraf

Ramírez-Angulo

López-Martín

et al. 2017

Circuit Theory & Apps

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A scheme to achieve simultaneously extremely high slew-rate improvement and avoiding open-loop gain degradation in one-stage super class AB op-amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high-output current enhancement factors at the expense of degrading the open-loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew-rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180-nm complementary metal-oxide semiconductor technology with open-loop gain of 67 dB, a factor 2 improvement in GBW, and a current enhancement factor of 270 verify the proposed scheme.

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A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays

Cited by 13 publications

References 25 publications

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

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