A Low Power High Performance Radix-4 Approximate Squaring Circuit

Datla, Satyendra; Thornton, Mitchell A.; Matula, David W.

doi:10.1109/asap.2009.35

Cited by 18 publications

(4 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…10, the delay and power of the proposed architecture have been compared with the Radix-4 Booth encoded squarer architecture for bit size n ≥ 64. Furthermore, application specific integrated circuit (ASIC) design has been performed for 8,12,16 and 32 bit squaring architectures using Cadence Spectre Virtuoso 6.1.4 with 180 nm technology with 1.8 V DC power supply. The device parameters are contained in gpdk180 model file.…”

Section: Resultsmentioning

confidence: 99%

“…As a result of that the circuit complexity, power requirement and also the propagation delay due to larger gate count increase drastically [8]. Thus, the task to design the squarer units with less complexity has attracted the attention of the researchers [8][9][10][11][12][13][14][15]. In [13], the method improved the squarer design by developing the folding technique first proposed in [10].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A New Squarer design with reduced area and delay

Banerjee

Das

2016

IET Computers & Digital Techniques

View full text Add to dashboard Cite

Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less amount of hardware, propagation delay and power consumption. Our work proposes an efficient algorithm using literals minimisation technique to achieve squaring with improved performance with respect to area, delay and power. This technique compares favourably with the recent work by offering less gate delay, transistor count and area. The proposed optimisation algorithm has been verified using different Xilinx and Altera Field Programmable Gate Array device family. Simulation results show better performance of our technique than the work shown in the past work in respect of delay, power and area. Moreover the proposed technique has been compared with the well known Radix-4 Booth encoded squarer technique. Further, application specific integrated circuit (ASIC) implementation has been performed and the performance parameters have been compared with the earlier work and that also establishes the better results for our technique.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A New Squarer design with reduced area and delay

Banerjee

Das

2016

IET Computers & Digital Techniques

View full text Add to dashboard Cite

show abstract

“…Furthermore, the design utilizes shared circuitry among the floating-point squarer and multiplier circuits to minimize impact due to area increases. If a unit-in-the-last-place (ulp) accurate approximation is the accepted rounding method for the system, a left-to-right approximation squarer such as the one presented in [8,9,10] would be the best choice since floating point circuits only use the n most significant bits if truncation is used. This approach however is not a feasible option because all the IEEE rounding methods are implemented in the floating-point multiplier in [2].…”

Section: Introductionmentioning

confidence: 99%

Low power floating-point multiplication and squaring units with shared circuitry

Moore

Thornton

Matula

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

Self Cite

View full text Add to dashboard Cite

Abstract-An architecture for a combinational floating point multiplier and squarer is described for the purpose of producing a low power floating point square with small area requirements. The floating-point multiplier and squarer architecture are compared to demonstrate the power advantage of the squarer. The multiplier and squarer are combined into one circuit in order to take advantage of the squarer power improvements with a minimal increase in area. Shared circuitry among the units provides justification for inclusion of a dedicated squarer since a small amount of additional circuitry is required and the power savings for squaring computations is significant as compared to the use of a general-purpose multiplier to generate a squared value.

show abstract

“…Squaring operations are common in many applications such as floating point divide and square-root [1], cryptography, computation of Euclidean distance among nodes in graphic processing, and rectangular to polar conversion. [7] In many DSP applications the squaring operation is the most commonly used powering operation compared to other higher powering operations. Hence targeting the most commonly used operations would result in maximum savings in terms of area and power.…”

Section: Introductionmentioning

confidence: 99%

Squaring units and a comparison with multipliers

Deshpande

Draper

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

View full text Add to dashboard Cite

Abstract-Power is becoming a precious resource in modern VLSI design, even more so than area. With large number of applications requiring support of functional units like squares, cubes and other higher order units, it becomes imperative that such functions be implemented in hardware. Implementing those functions using existing general-purpose multipliers in a design may be economical in terms of area but requires more power consumption than is necessary. We propose to use dedicated squaring units to perform squares. We study the tradeoffs of using a dedicated squaring unit compared with a general-purpose multiplier designed with Radix-4 Modified Booth encoding scheme. We compare area and power requirements for different widths. We are able to reduce power consumed per computation by more than 50% with this approach. Moreover, when an application demands a large number of squaring operations compared to multiplies, there is a strong case for using multiple squaring units for performing multiplication.

show abstract

A Low Power High Performance Radix-4 Approximate Squaring Circuit

Abstract: Abstract

Cited by 18 publications

References 21 publications

A New Squarer design with reduced area and delay

A New Squarer design with reduced area and delay

Low power floating-point multiplication and squaring units with shared circuitry

Squaring units and a comparison with multipliers

Contact Info

Product

Resources

About