A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System

Abstract

In this paper, a low-power high-speed CMOS full adder core is proposed for embedded system. Based on a new three-input exclusive OR (3-XOR) design, the new hybrid full adder is composed of pass-transistor logic and static CMOS logic. The main design objectives for the full adder core are providing not only low power and high speed but also with driving capability. Using TSMC CMOS 0.35-µm technology, the characteristics of the experimental circuit compared with prior literature show that the new adder improves 1.8% to 35.6% in power consumption, 11.7% to 41.2% in time delay of Co, and 13.7% to 91.4% in power-delay product of Co. The circuit is proven to have the minimum power consumption and the fastest response of carry out signal among the adders selected for comparison. Due to the low-power and high-speed properties, both the new exclusive OR circuit and the new full adder can be efficiently integrated in a system-on-a-chip (SoC) or an embedded system.

A Regularly Modularized Multiplexer-based Full Adder for Arithmetic Applications

“…However, the full-swing full adders have no output driver in design leading to signal attenuation problems when they are connected in series to construct multi-bit adders. Therefore, many studies focus on gathering many features such as full-swing voltage, powerful output driving capability and good power delay product [9,10,11,12,13] in the meantime to boost the performance of full adder circuit design as a whole. However, the penalties have to pay for taking too many design issues into consideration are increased circuit complexity, larger chip area, difficult layout design, and increased transistor count.…”

A Study of Hybrid Full Adder for Low Power and High Speed Applications

“…There are number of logic styles having different performance parameters where each of them has certain specialties. In the conventional domain some of the best design styles being accommodated are dynamic CMOS logic, transmission gate full adder (TGA), static complementary metal-oxide-semiconductor (CMOS) and complementary pass-transistor logic (CPL) [4]. Hybrid logic design style is also there which is being used by some other adders having integration of more than one logic style.…”

“…Through this the latency was reduced to much higher extent and thus a carry ahead header was designed which consumed very less power and where the speed was very high. [4]BalakrishnaBatta et al (2012)In this paper entertained with the fact that to design the low power circuitry, one of the best present techniques was the GDI technique. The digital circuit designed on the basis of this technique enabled the reduction in the amount of power being consumed along with the transistor count of the digital circuit and the propagation delay.…”

“…It is actually the rate through which energy is being transferred from certain source to the device in use. Power dissipation [4] acts as an actual hurdle in designing any device. There are many reasons why this issue is emerging these days.…”

Design of Low Power and Area Efficient Full Adder for ALU Using 90nm Process for Industrial Based CAD/CAM Manufacturing Units

“…Its look like a static CMOS inverter but it differs because the GDI cell [11] has two extra inputs as shown in Figure- From truth table of a full adder, we can consider that, when Cin = 0, the full adder Cout is equal to A AND B otherwise it is equal to A OR B. By, using multiplexer Cout is selected.…”