A low-power high-speed true single phase clock divide-by-2/3 prescaler

Abstract

Abstract:A novel low power high-speed true single-phase clockbased (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18 µm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10 GHz with 1.836 mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8 GHz with 1.34 mW power consumption.

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

“…The conventional 2/3 prescaler proposed in [7], shown in Fig. 2, can improve the division speed with reduced power consumption.…”

“…With the improved speed of the MOS devices, in several GHz applications, the current-mode-logic (CML) divider can be replaced with the true single-phase clocked (TSPC) logic to reduce the power consumption. Several TSPC prescaler topologies have been proposed to offer high speed and low power [3,4,5,6,7]. In [5] a dual-modulus divide-by-2/3 prescaler exploiting the forced-discharging method in the second branch of a TSPC flip-flop, can substantially improves the maximum speed of the standalone prescaler.…”

“…And in [6], one of the branches of TSPC D flip-flops is merged based on this circuit, to further reduce the power consumption. Alternatively, a charge-control technique in the DFF branch is proposed to eliminate the short current in divide-by-3 mode [7].…”

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

“…However, they have a small input frequency locking range and limited output swing. Dual-modulus prescaler based on True-singlephase clock (TSPC) D-flip-flops (DFFs) is widely utilized in several GHz for its low power, small area, wide operating frequency range, and large output swing [5,6,7,8,9]. These designs can be further enhanced by using ETSPC prescalers which eliminate one transistor in each stage.…”

“…Improving the speed of TSPC prescaler with less power penalty is the key issue. Several techniques have been developed, including decreasing the threshold voltage of nMOS transistor [5], reducing the critical path delay [6,7], minimizing the logic gates [8,9,11], shutting down the unused block [10]. In this letter, we present a design technique that improves the speed of TSPC prescalers without a power penalty.…”