A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor

Abstract

As a result of advances in technology shrinking device dimensions, the occurrence of transient errors is increasing. This together with the concomitant reduction in supply voltages has decreased noise margins causing system reliability to be reduced, at a time when electronic systems are being used increasingly in 'safety critical' applications. Previous work has demonstrated that an information redundant Concurrent Error Detection (CED) scheme using Dong's Code can be applied efficiently to a processor using an asynchronous design style incurring area overheads of approximately 12% [1] when placed on silicon. This paper furthers the above work by extending the capabilities of the processor to include the multiplication function also guarded by a CED scheme, permitting the processor to be used in a wider range of applications; e.g. DSP. The paper also demonstrates that a reduction in power of 22% can be achieved by utilising an asynchronous design style rather than its synchronous counterpart. Furthermore, the power overhead for the asynchronous CED processor was found to be 5% less than that of the synchronous processor without CED. Asynchronous design style is also known to have the inherent benefit of not requiring difficult to design, global timing clock trees and networks. Previous work has also demonstrated that approximately, 25% area savings can be made when comparing Dong's Code to a Berger Code CED scheme on the multiplier function [2]. Through the implementation of a larger number of operations within the ALU, all protected by the same information redundant code, further savings can be made through reuse of common blocks, as codes often share many similarities within their prediction equations. With lower power dissipation and a reduced area overhead, compared to its synchronous counterpart, this makes the asynchronous CED circuit attractive and viable for reliable mobile computation. This paper also extends the work with the implementation of a synchronous and asynchronous processor, with and without CED on a FPGA.

Optimising Self-Timed FPGA Circuits

“…Most have opted for a delay insensitive encoding scheme to absorb the delay variation at the expense of resources. In recent times there have been a few research projects [7], [8], [9] that have followed variations of the third approach to produce asynchronous implementations of small 5 stage pipeline RISC processors. Marshall [9] began from an asynchronous gate level description and converted each gate into the equivalent Xilinx primitive block.…”