A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

Zhang, Heng; Fan, Xiaopeng; Sinencio, Edgar Sanchez

doi:10.1109/jssc.2008.2011033

Cited by 233 publications

(104 citation statements)

References 23 publications

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“…The input impedance seen from RFin of LNA is the same with and without the linearization circuit (L.C.) refered from [4]. The degradation in gain and current consumption is not severe because the transconductance and bias current of the linearization circuit are much smaller than those of the cascode stage.…”

Section: Detail Of Cmos Lnamentioning

confidence: 99%

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Temperature Analysis of Lna With Improved Linearity for Rf Receiver

Shimpi¹,

Subramaniam²,

Gogate³

2014

IJRET

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Section: Detail Of Cmos Lnamentioning

confidence: 99%

“…Another linearization method, post-linearization technique, is introduced by Zang, H., X. Fan, and E. S. Sinencio [4]. This linearization technique uses a diode connected NMOS transistor to apply to a cascode common gate (CG) LNA, and the linearity performance looks good.…”

Section: Introductionmentioning

confidence: 99%

Temperature Analysis of Lna With Improved Linearity for Rf Receiver

Shimpi¹,

Subramaniam²,

Gogate³

2014

IJRET

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“…Ultra-wideband technology using the unlicensed frequency band from 3.1 to 10.6 GHz has become much interested in broadband wireless communication recently [1,2]. UWB technology can be found in many applications nowadays such as sensor networks, vehicular and ground penetrating radars, radio-frequency identification (RFID) and short range wireless communication systems like wireless personal area network (WPAN), wireless body area network (WBAN) [3].…”

Section: Introductionmentioning

confidence: 99%

“…Full UWB-band LNAs designed using several topologies have recently been published, such as distributed amplifiers [4], feedback amplifiers [5,6], common gate [7,2,8], or LC ladder filters LNA [1]. With technology scaling, short channel devices suffer from poor linearity as the low supply voltage is mandated and due to high field mobility effect.…”

Section: Introductionmentioning

confidence: 99%

A 1V folded common-gate CMOS LNA for full UWB band

Phan

Farrell

2009

IEICE Electron. Express

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This paper presents a low voltage 2.8-11.2 GHz CMOS broadband low noise amplifier (LNA) using folded common-gate (CG) topology. The broadband input matching is achieved by adopting CG topology. Bandwidth extension is proposed by inserting an inductor to create a broadband band-pass characteristic with a choke inductor. A folded topology is employed to reduce the supply voltage and thus power consumption. A source follower jointly acts as the buffer stage for broadband output impedance matching and feed-forward path for gain enhancement. Maximum power gain is 11.2 dB and the NF ranges from 2.58 to 4 dB over the full band. The LNA achieves an average IIP3 of −6.5 dBm while consumes only 4.6 mW. The proposed broadband LNA is designed in 0.18-μm CMOS process from 1 V supply.

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“…입력 정합 회로는 cascode 구조로도 고안할 수 있지만, 기생성분은 입력 정합의 변화로 이어질 수 있다. Common gate 구성은 쉽게 넓은 입력 임피던스 정합에 사용될 수 있다 [15] . …”

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Highly Linear Wideband LNA Design Using Inductive Shunt Feedback

Jeonng¹,

Cho²

2013

The Journal of Korean Institute of Electromagnetic Engineering

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Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in 0.18 μm CMOS process, the chip area of this LNA is 0.202 mm 2 , including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7～8 dB over 1.5～13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

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A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

Cited by 233 publications

References 23 publications

Temperature Analysis of Lna With Improved Linearity for Rf Receiver

Temperature Analysis of Lna With Improved Linearity for Rf Receiver

A 1V folded common-gate CMOS LNA for full UWB band

Highly Linear Wideband LNA Design Using Inductive Shunt Feedback

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