A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection

Hasib-Al-Rashid,; Manjunath, Nitheesh Kumar; Paneliya, Hirenkumar; Hosseini, Morteza; Hairston, W. David

doi:10.1109/isqed48828.2020.9137056

Cited by 16 publications

(12 citation statements)

References 16 publications

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“…Thanks to the ultra-low static power (at µW scale) of this FPGA, the overall power consumption during inference is approximately equal to the dynamic power of the FPGA, which is 17 mW. The energy efficiency is increased to 3.9 GOP/J, while the throughput is slightly improved to 0.067 GOP/s due to the same parallelism strategy they applied as in [6].…”

Section: Related Workmentioning

confidence: 97%

“…Recently, researchers have started considering the energy efficiency of ondevice FPGA accelerators. In 2020, Hasib-Al-Rashid et al [6] proposed a LSTM processor for FPGA XC7A100T from Artix-7 family. Their design only utilises 1% of LUTs, 9% of BRAM and 1.67% of DSP slices of this FPGA by extremely reusing the hardware resources, such as only implementing two multiplication and accumulation (MAC) units in the LSTM cell.…”

Section: Related Workmentioning

confidence: 99%

“…In both works [4,6], researchers applied fixed-point logic to simplify the design and reduce the loss of precision compared to aggressive quantisation. The activation functions tanh() and sigmoid() were replaced with hard tanh() and hard sigmoid() respectively, which simplifies the computations but leads to a large reduction of precision [10].…”

Section: Related Workmentioning

confidence: 99%

“…how many neurons are necessary to represent it. Commonly used hidden sizes include 1 [5], 12 [6], 32 to 256 [13]. In our application case we use a hidden size of 20.…”

Section: Lstm Model Vs Layer Vs Cellmentioning

confidence: 99%

See 3 more Smart Citations

Enhancing Energy-Efficiency by Solving the Throughput Bottleneck of LSTM Cells for Embedded FPGAs

Qian

Ling

Schiele

2023

Communications in Computer and Information Science

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To process sensor data in the Internet of Things(IoTs), embedded deep learning for 1-dimensional data is an important technique. In the past, CNNs were frequently used because they are simple to optimise for special embedded hardware such as FPGAs. This work proposes a novel LSTM cell optimisation aimed at energy-efficient inference on end devices. Using the traffic speed prediction as a case study, a vanilla LSTM model with the optimised LSTM cell achieves 17534 inferences per second while consuming only 3.8 µJ per inference on the FPGA XC7S15 from Spartan-7 family. It achieves at least 5.4× faster throughput and 1.37× more energy efficient than existing approaches.

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Section: Related Workmentioning

confidence: 97%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…how many neurons are necessary to represent it. Commonly used hidden sizes include 1 [5], 12 [6], 32 to 256 [13]. In our application case we use a hidden size of 20.…”

Section: Lstm Model Vs Layer Vs Cellmentioning

confidence: 99%

See 2 more Smart Citations

Enhancing Energy-Efficiency by Solving the Throughput Bottleneck of LSTM Cells for Embedded FPGAs

Qian

Ling

Schiele

2023

Communications in Computer and Information Science

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“…Several works perform EEG artifact rejection, each focusing on different areas of artifacts. Common methods for artifact detection and rejection includes common average reference (CAR) [272], independent component analysis (ICA) [199], high amplitude rejection [218,273,274], wavelet transforms [275], CNN [223], and LSTM [276]. We summarized existing literature on artifact detection and rejection in Table 2.2.…”

Section: Automated Artifact Detectorsmentioning

confidence: 99%

Deep learning methods for diagnosis of epilepsy from electroencephalograms

Peh¹

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Performance Evaluation of FPGA-Based LSTM Neural Networks for Pulse Signal Detection on Real-Time Radar Warning Receivers

Tekincan

Ayyıldız

2022

The Computer Journal

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Radar warning receivers are real-time systems used to detect emitted signals by the enemy targets. The conventional method of detecting the signal is to determine the noise floor and differentiate the signals above the noise floor by setting a threshold value. The common methodology for detecting signals in noisy environment is Constant False Alarm Rate (CFAR) detection. In CFAR methodology, threshold level is determined for a specified probability of false alarm. CFAR dictates the signal power to be detected is higher than the noise floor, i.e. signal-to-noise ratio (SNR) should be positive. To detect radar signals for negative SNR values machine learning techniques can be used. It is possible to detect radar signals for negative SNR values by Long Short-Term Memory (LSTM) Artificial Neural Network (ANN). In this study, we evaluated whether LSTM ANN can replace the CFAR algorithm for signal detection in real-time radar receiver systems. We implemented a Field Programmable Gate Array (FPGA) based LSTM ANN architecture, where pulse signal detection could be performed with 94% success rate at -5 dB SNR level. To the best of our knowledge our study is the first where LSTM ANN is implemented on FPGA for radar warning receiver signal detection.

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A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection

Cited by 16 publications

References 16 publications

Enhancing Energy-Efficiency by Solving the Throughput Bottleneck of LSTM Cells for Embedded FPGAs

Enhancing Energy-Efficiency by Solving the Throughput Bottleneck of LSTM Cells for Embedded FPGAs

Deep learning methods for diagnosis of epilepsy from electroencephalograms

Performance Evaluation of FPGA-Based LSTM Neural Networks for Pulse Signal Detection on Real-Time Radar Warning Receivers

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