A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter

Abstract

This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

Wide-range energy-efficient buffer-based voltage level-up converters for multi-supply voltage systems

“…Many buffer-based LCs are discussed in the literature [7][8][9][10][11]; among them the LC in [7] uses dual-supply voltage buffer structure. To offset the threshold drop at the output node, a separate inverter is used to drive two keeper PMOS devices.…”

“…Although with certain modifications in the buffer it takes less propagation delay, it consumes more power and silicon area. The reduced swing inverter [8] is utilized along with Drain-Induced Barrier Lowering (DIBL) and body effect [9] at the output to minimize the static current. However, due to the diode-connected NMOS, it fails to take care of the input inverter, which produces static current.…”

“…A noteworthy mention is that the buffer-based LC can also be used with single supply voltage [2,3,9] without degrading the circuits performance. It makes the circuit less complex and lowers complications in supply voltage routing.…”

“…It makes the circuit less complex and lowers complications in supply voltage routing. This enables effective physical design through flexible placement with the buffer LCs [9]. Hence LC circuits with single-supply voltage based on the buffer structure, namely TGBLC and SPBLC, are proposed.…”