A low-power Read-Out Circuit and low-cost assembly of nanosensors onto a 0.13 μm CMOS Micro-for-Nano chip

Abstract

This paper describes the Micro-for-Nano (M4N) approach as effective solution to overcome challenges related to the nanomaterial assembly with electrodes, the low-noise measurement of nanomaterial electrical properties and the CMOS design of the nanosensor electronic interface. This paper presents both the fabrication process of a nanodevice onto the IC surface using Dielectrophoresis (DEP) and the ReadOut Circuit (ROC) used for the inspection of the electrical properties of nanowires (NW). The ROC includes a Time-overThreshold circuit which has been characterized stand-alone. It shows maximum measurement error of 0.8% with a maximum linearity error below 1.86% in the range 300 kΩ-100 MΩ. The ROC occupies 0.0067 mm 2 silicon area and simulation data shows that the maximum power consumption is 8.9 µW at 1.2 V. The paper presents first measurement results obtained on fabricated prototype chips based on ZnO-NW.

pH-triggered conduction of amine-functionalized single ZnO wire integrated on a customized nanogap electronic platform

“…The innovation of the presented approach lies in the integration of the single amine-functionalized wires on a nanogap electrode chip and the parallel current–voltage characterization and pH sensing measurements of the eight ZnO-gold junctions. This can be the first step toward a smart and portable micro-chip sensor [ 31 ]. The ease and reproducible synthesis of the functionalized ZnO wires as well as on the cost-effective and simple fabrication of the nanogap electrode chip are also further advantages of the presented system.…”

A Low-Power 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS IC for ZnO-Nanowire Assembly and Nanowire-Based UV Sensor Interface

“…Hence, the ROC is conceived for measuring the electrical properties of the nanomaterial in the first and third quadrant, separately. The final aim concerning an high-density nanosensor and ROC array (about 100 elements per mm 2 ) requires both an accurate fabrication process [17] and a challenging design of the ROC in term of power consumption, silicon area and impedance measurement. The conceived QDIC is thus described within the next section.…”

“…On the contrary, our Micro-for-Nano (M4N) approach [17] is conceived to set fast assembly process exploiting DEP technique to integrate nanomaterials in a high-density array directly on top of CMOS interfaces (similarly to a Charge Coupled Device sensor, see Fig. 1).…”

“…Since the DEP is a low complexity but effective process, it is widely used to "attract and orient" nanomaterials in solution and, consequently, it is the best solution for driving NWs integration on CMOS technology process. Using an external DEP source [17], the AC signal would need to pass through the pads of the chip to be applied to the AlTEs, leading to a series of additional processing issues. Indeed, the electric field will be generated in the integration area as well as in proximity of the pads, so that nanomaterials in solution will also move towards the boundary of the chip, reducing the probability of integration on AlTEs.…”