A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

Abstract

SUMMARYA novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 μW at 1.8 V power supply and 1 GHz clock frequency.

Low-power 4-bit flash analogue to digital converter for ranging applications

“…An approach to reduce kickback noise is proposed in [3]. By adding transistors M n4 and M n5 in Fig.…”