A low-power register file based on access queues for multi-issue processors

Abstract

Multi-port register file is a critical component of high-performance multi-issue processors to exploit instruction parallelisms. However, multiple ports cause such problems as high power and large area. In this paper, we present a novel multi-bank register file (MBRF) architecture to reduce register ports as well as its power and area, which is based on register access queues. The proposed architecture organizes a read queue and a write queue for each register bank, and buffers all the register operations from instructions into the access queues, thus avoiding bank conflicts. At the same time, we use both combine and forward assignment strategies to reduce read and write requests for register file. Experimental results show our techniques are more advantageous in both performance and power saving than the traditional MBRF, achieving 52% and 47% power saving for integer and floating-point programs respectively, with only 1.6% and 2.8% IPC loss.