A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric

Geissler, S.; Appenzeller, D.; Cohen, E.; Charlebois, Serge A.; Kartschoke, P.; McCormick, P.; Rohrer, Norman J.; Salem, G.; Sandon, Peter A.; Singer, Ben; Reyn, T. Von; Zimmerman, J.

doi:10.1109/isscc.2002.992979

Cited by 14 publications

(6 citation statements)

References 3 publications

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“…Researches in [9][10] give designs to reduce the dynamic frequency scaling to zero or nanosecond level. Therefore, the latency of PSU degree switch becomes comparable to a pipeline flush, which can be finished in tens cycles.…”

Section: Baseline Technique and Related Workmentioning

confidence: 99%

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Miwa

Shimada

et al. 2011

J. Comput. Sci. Technol.

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Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.

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Section: Baseline Technique and Related Workmentioning

confidence: 99%

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Miwa

Shimada

et al. 2011

J. Comput. Sci. Technol.

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“…PowerPC 750 [7] [11] uses a dual PLL architecture which allows fast DFS with effectively zero latency (one processor clock cycle is being skipped). With the benefit of such PLL architecture, there is almost no transition overhead associated with changing the operating clock frequency [11] when resizing the RF. It should also noted that this technique has a fairly simple implementation and does not add significant complexity to the embedded processor pipeline, since the scheduler in embedded processors already keeps track of miss load instructions in L2 caches.…”

Section: Dynamic Register File Resizingmentioning

confidence: 99%

“…Such a dynamic frequency scaling (DFS) should be done fast, otherwise it can negatively impact performance during dynamic RF resizing. In our studied processor, IBM PowerPC 750FX, DFS is done in effectively zero cycle using a dual PLL architecture [11]. The RF size adaptation is realized using a circuit modification scheme that comes with minimal hardware modification, unlike costly banking or clustering techniques.…”

Section: Introductionmentioning

confidence: 99%

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Homayoun

Pasricha

Makhzan

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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With CMOS scaling leading to ever increasing levels of transistor integration on a chip, designers of high-performance embedded processors have ample area available to increase processor resources in order to improve performance. However, increasing resource sizes can increase power dissipation and also reduce access time, which can limit maximum achievable operating frequency. In this paper, we explore optimizations for the processor register file (RF), to improve performance and reduce the energy-delay product. We show that while increasing the size of the RF can potentially increase the IPC, overall it results in an increase in program execution time. In response we propose L2MRFS -a dynamic register file resizing scheme in tandem with frequency scaling, which exploits L2 cache misses to noticeably improve processor performance (11% on average) and also significantly reduce the energy-delay product (7%).

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“…One example is a recent embedded PowerPC 750, which employs three threshold voltages: high, standard, and low. The low threshold transistors account for only 5% of the total transistor width, but around 50% of the total leakage [7]. Several techniques have been developed to reduce leakage current from transistors on the critical path.…”

Section: Dynamically-deactivated Fast Transistorsmentioning

confidence: 99%

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Heo¹,

Barr²,

Hampton³

et al. 2002

SIGARCH Comput. Archit. News

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A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric

Cited by 14 publications

References 3 publications

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Dynamic fine-grain leakage reduction using leakage-biased bitlines

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