A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Ming, Xin; Zhou, Zekun; Zhang, Bo

doi:10.1007/978-3-642-32770-4_3

Cited by 7 publications

(6 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The main improvements proposed over the years to the circuit in [2] are briefly analysed in the followings. In [3] the input stage was doubled and adaptive biasing was employed to speed up the LDO response to transients. The same authors introduced in [4] a slew-rate enhancement circuit, realized by embedding an RC network into the current mirrors within the main Gm cell of the EA.…”

mentioning

confidence: 99%

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only 0.7µA quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in 1µs the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figureof-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

show abstract

mentioning

confidence: 99%

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…Ref. [14] This work LDO comes into the current limit mode induced by the dropout voltage being lower than jV TP j. The reason for I OUT declining to 170 mA is that the LDO enters into the short circuit mode at that time.…”

Section: Resultsmentioning

confidence: 93%

A micro-power LDO with piecewise voltage foldback current limit protection

Hailong¹,

You-bao²,

Guo³

et al. 2012

J. Semicond.

View full text Add to dashboard Cite

To achieve a constant current limit, low power consumption and high driving capability, a micro-power LDO with a piecewise voltage-foldback current-limit circuit is presented. The current-limit threshold is dynamically adjusted to achieve a maximum driving capability and lower quiescent current of only 300 nA. To increase the loop stability of the proposed LDO, a high impedance transconductance buffer under a micro quiescent current is designed for splitting the pole that exists at the gate of the pass transistor to the dominant pole, and a zero is designed for the purpose of the second pole phase compensation. The proposed LDO is fabricated in a BiCMOS process. The measurement results show that the short-circuit current of the LDO is 190 mA, the constant limit current under a high drop-out voltage is 440 mA, and the maximum load current under a low drop-out voltage is up to 800 mA. In addition, the quiescent current of the LDO is only 7 A, the load regulation is about 0.56% on full scale, the line regulation is about 0.012%/V, the PSRR at 120 Hz is 58 dB and the drop-out voltage is only 70 mV when the load current is 250 mA.

show abstract

“…A popular error amplifier (EA) employed in fast LDO designs for its excellent dynamic behavior is the class-AB common-gate EA proposed in [4]. The topology was further improved by employing recycling techniques [5][6][7][8][9][10], local common-mode feedback [7,[10][11][12][13], and by a more efficient frequency compensation circuit [10]. Despite its speed, the class-AB input EA is not a suitable candidate for the application envisaged here due to its large offset voltage, caused by inherent mismatches within the input stage.…”

Section: Logicmentioning

confidence: 99%

High-Precision Low-Temperature Drift LDO Regulator Tailored for Time-Domain Temperature Sensors

Răducan

Grăjdeanu

Ţopa

et al. 2022

Sensors

View full text Add to dashboard Cite

This paper proposes a high-precision LDO with low-temperature drift suitable for sensitive time-domain temperature sensors. Its topology is based on multiple feedback loops and a novel approach to frequency compensation, that allows the LDO to maintain a large DC gain while handling capacitive loads that vary over a wide range. The key design constraints are derived by using a simplified, yet intuitive and effective, small-signal analysis devised for LDOs with multiple feedback loops. Simulation and measurement results are presented for implementation in a standard 130 nm CMOS process: the LDO outputs a stable 1 V voltage, when the input voltage varies between 1.25 V to 1.5 V, the load current between 0 and 100 mA, and the load capacitor between zero and 400 pF. It exhibits a DC load regulation of 1 µV/mA, a 288 µV output offset with a standard deviation of 9.5 mV. A key feature for the envisaged application is the very low thermal drift of the output offset: only 14.4 mV across the temperature range of −40 °C to +150 °C. Overall, the LDO output voltage stays within +/−3.5% of the nominal DC value over the entire line voltage, load, and temperature ranges, without trimming. The LDO requires only 1.4µA quiescent current, yet it provides excellent responses to load transients. The output voltage undershoot and overshoot caused by the load current jumping between 0 and 100 mA in 1 µs are: 10%/22% for CL = 0 and 12%/16% for CL = 400 pF, respectively. A comparative analysis against seven LDOs published in the last decade, designed for similar levels of supply voltage and output voltage and current, shows that the LDO presented here is the best option for supplying sensitive time-domain temperature sensors. The smallest thermal drift of the output offset, smaller than +/−15 mV, that is, 6.7 times smaller than its closest competitor, and the best overall performance when PSR up to 1 kHz, was considered.

show abstract

A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Cited by 7 publications

References 25 publications

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

A micro-power LDO with piecewise voltage foldback current limit protection

High-Precision Low-Temperature Drift LDO Regulator Tailored for Time-Domain Temperature Sensors

Contact Info

Product

Resources

About