A Low Power VLSI Implementation of Reconfigurable FIR Filter  Using Carry Bypass Adder

Reddy, K. Rahul; Suresh, H. N.

doi:10.22266/ijies2018.0430.25

Cited by 3 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The sampling period and area complexity were reduced. It used a faster bit clock for carrying save accumulation, but that used a very slower clock for remaining FIRF operations Reddy et al [24] A low-power adaptive FIRF based on the DA algorithm The least mean squares (LMS) algorithm reduced the mean squared error (MSE) between filter output and the desired response. This technique used a carry-save accumulator for FIRF architecture.…”

Section: Methodsmentioning

confidence: 99%

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

View full text Add to dashboard Cite

Finite impulse response (FIR) filter implementations abound and play a major part in signal processing applications. The FIR filter (FIRF) delivers several benefits, and there exist many different realizations, such as designs using a system generator, normal FIRF, decimator FIRF, genetic algorithm (GA)-based, and parallelbased, among others. Most architectures utilize more hardware with less efficiency. Moreover, these existing architectures did not concentrate on and explored the applications' characteristics. The FIRF affords several paybacks like (i) computational efficiency in multi-rate frameworks, (ii) manageable linear phase response, and (iii) the desirable numerical ability to accomplish finite precision and fractional arithmetic. The digital multi-standard RFIR filter is implemented in wireless applications to decrease the bit error rate (BER). The discrete FIRF can render efficient designs with low-power consumption and high performance. Earlier, hordes of research articles described different FIRF designs without handling signal denoising with an effective multiplier design. Booth's algorithm performs multiplication by multiplying two signed binary numbers in 2's complement notation. The Booth multiplier (BM) overcomes the reduced area drawback, but it would not work with alternation of zeros and ones since it entails more additions and subtractions [1-3]. This problem is overcome by the modified BM (MBM), which contains half the number of partial product rows. It functions well regarding speed and power consumption. On the other hand, its main shortcoming is sloppy work for negative numbers [4, 5].

show abstract

Section: Methodsmentioning

confidence: 99%

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

View full text Add to dashboard Cite

show abstract

“…In carrying out the bulk of the numerical operations, for example, the adders, which are among the arithmetic and logic units (ALUs), are used [15]. The delay from such systems often has a fundamental task of deciding the replication of the operating clock by the processors.…”

Section: Literature Reviewmentioning

confidence: 99%

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

2023

Teh. vjesn.

View full text Add to dashboard Cite

This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utilization of reconfigurable Kogge Stone-dependent hybrid adder structures, now referred to as KS-CPA, in which reconfiguration occurs during the addition operation. The Least Significant Bits (LSB) are processed using a carry propagate adder, while the Most Significant Bits (MSB) are computed using the Kogge Stone adder. Depending on the data width and deviceaccessible energy resources, the hybrid configuration of the adder offers the 4-bit, 8-bit, and 16-bit addition. The adder form is identified by a shift in the configuration of its Carry Look-ahead and then by a Kogge Stone Adder (KSA). Throughout the activity, the KS-CLA crossbreed configuration is used to attain the fastest speed and low energy usage. The effectiveness, including its proposed hybrid adder, is evaluated by looking at the speed, energy, and area parameters, including a suitable area use during rapid applications in which both less delay and low power adders are required. Considering these, we are structuring an IoT processor that can be reconfigured to gain from SIMD. We have demonstrated that our hybrid adder-enhanced processor saves energy up to 13% and reduces 27% latency. The proposed 16 and 32-bit adders will boost time, power, and Area Delay Product (ADP) by almost 18-24% and 13-19% respectively.

show abstract

“…Eventually, i.e., LS 0 = 0100; LS 1 = 0010; LS 2 = 0101; LS 3 = 1000. These shifted outputs are performed as the 2 s complement, which is given in Equations ( 8)- (11).…”

Section: Examplementioning

confidence: 99%

“…The traditional FIR filter design suffers from a major hindrance related to the number of evaluation processes, which is too high, so that it utilizes a higher filter order, larger area of the hardware, and consumes more energy when compared to the reconfigurable FIR filter [6,7]. In the conventional design, the FIR filter was implemented with the Distributed Arithmetic (DA) technique, in which the filter order increased with higher level [8][9][10][11]. Many of the existing architectures have been designed by using various types of FIR filter, such as: the linear-based FIR filter [12], parallel-based FIR filter [13], low-power-multiplier FIR filter [14], and DA-based FIR filter [15].…”

Section: Introductionmentioning

confidence: 99%

“…Xilinx 14.4 ISE was also used during experiments with the "Generate programing file" option.The results of the area, power, and delay performance of the 4-bit design are described in Table4. In this comparison, DA[7], CBA[9], and R2 designs are considered as a reference and compared with the proposed filter design. RFIR-R2-CSLA, RFIR-R2-LCSLA, and RFIR-VM-CLA architectures were previously implemented by the same author, and the results are also compared with the current proposed method.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

Reddy¹,

Madhavan²,

Falkowski-Gilski

et al. 2022

Electronics

View full text Add to dashboard Cite

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

show abstract

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder

Cited by 3 publications

References 12 publications

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

Contact Info

Product

Resources

About