A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

Limpisawas, Tanachai; Wattanapanitch, Woradorn

doi:10.1109/access.2022.3185630

Cited by 6 publications

(2 citation statements)

References 41 publications

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“…Because OCL-LDO cannot compensate the loop through the zero point introduced by external ESR resistor and capacitor, it is necessary to design a special frequency compensation module. OCL-LDO has many frequency compensation methods, some commonly used methods are introduced in references [7][8][9][10][11][12]. The damping-factor-control (DFC) method redistributes the zero and pole points of the system by adding a damping control unit in the circuit.…”

Section: Introductionmentioning

confidence: 99%

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

Ning,

Guo,

Jia

et al. 2023

Electronics

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A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

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Section: Introductionmentioning

confidence: 99%

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

Ning,

Guo,

Jia

et al. 2023

Electronics

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show abstract

“…Traditional low-dropout regulators (LDOs) with large external output capacitors have been preferred for their superior load transient response; however, these configurations consume more area and are not suitable for system-on-chip (SoC) applications. Therefore, output-capacitor-less LDOs (OCL-LDOs) have emerged as the preferred architectures, aligning with the pursuit of efficiency and compactness [2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Serrano-Reyes,

Sanz-Pascual,

Calvo-López

2023

Electronics

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Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

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Design of transient enhanced output-capacitor-less flipped voltage follower based LDO regulator with a fast control loop for wide range of capacitive loads

Panigrahi

Mathew

2023

Microelectronics Reliability

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A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

Cited by 6 publications

References 41 publications

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Design of transient enhanced output-capacitor-less flipped voltage follower based LDO regulator with a fast control loop for wide range of capacitive loads

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