A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

Chen, Poki; Chen, Shiwei; Lai, Juan-Shan

doi:10.1109/asscc.2007.4425730

Cited by 15 publications

(2 citation statements)

References 11 publications

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“…However, typical duty cycle correctors occupy large areas due to their complicated structures and various component circuits, such as comparators, encoders and decoders, capacitors in the low-pass filter, or finite state machines (FSM) [1][2][3][4][5][6][7][8][9][10][11][12][13]. Therefore, it is strongly advised to implement a duty cycle corrector that consumes a small area.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

2021

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This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.

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Section: Introductionmentioning

confidence: 99%

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

2021

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“…The latter ones are recently dominant mainly due to ease of implementation in integrated circuits, but also because of high immunity to external disturbances and shorter conversion time than for analog methods. The most popular digital methods include pulse shrinking (or stretching) [18][19][20][21][22][23][24][25][26] and direct time coding based on the tapped delay line(s) [26,27]. The main advantage of the first method is the potential possibility to reach an infinitely high resolution.…”

Section: Introductionmentioning

confidence: 99%

A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines

Szplet¹,

Jachna²,

Kwiatkowski³

et al. 2013

Meas. Sci. Technol.

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We present the design, operation and test results of a time counter that has an equivalent resolution of 2.9 ps, a measurement uncertainty at the level of 6 ps, and a measurement range of 10 s. The time counter has been implemented in a general-purpose reprogrammable device Spartan-6 (Xilinx). To obtain both high precision and wide measurement range the counting of periods of a reference clock is combined with a two-stage interpolation within a single period of the clock signal. The interpolation involves a four-phase clock in the first interpolation stage (FIS) and an equivalent coding line (ECL) in the second interpolation stage (SIS). The ECL is created as a compound of independent discrete time coding lines (TCL). The number of TCLs used to create the virtual ECL has an effect on its resolution. We tested ECLs made from up to 16 TCLs, but the idea may be extended to a larger number of lines. In the presented time counter the coarse resolution of the counting method equal to 2 ns (period of the 500 MHz reference clock) is firstly improved fourfold in the FIS and next even more than 400 times in the SIS. The proposed solution allows us to overcome the technological limitation in achievable resolution and improve the precision of conversion of integrated interpolators based on tapped delay lines.

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Clock buffer with duty cycle corrector

Kao¹,

You²

2011

Microelectronics Journal

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A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

Cited by 15 publications

References 11 publications

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines

Clock buffer with duty cycle corrector

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