A low quiescent current power-on-reset circuit with configurable trip voltage

You, Heng; Zhou, Yumei; Qiao, Shushan

doi:10.1016/j.aeue.2022.154154

AEU - International Journal of Electronics and Communications

2022

DOI: 10.1016/j.aeue.2022.154154

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A low quiescent current power-on-reset circuit with configurable trip voltage

Heng You¹,

Yumei Zhou

Shushan Qiao

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2024

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Cited by 2 publications

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A Scalable Delay‐Expanding Technique for Low‐Area On‐Chip Power‐On Reset Circuits

Mansoury,

Saeedi,

Atarodi

2024

Circuit Theory & Apps

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A scalable structure is presented and analyzed that can provide delays in a wide range (microseconds to minutes) for the power‐on reset circuit. The proposed structure enables the implementation of these delays entirely on‐chip through the utilization of a provisional oscillator and a set of flip‐flops. The optimal number of flip‐flops can be determined through an area optimization process. The proposed power‐on reset circuit thresholds demonstrate the process, voltage, temperature (PVT) tolerance, facilitated by the use of resistors of the same type. Notably, the thresholds and provided delay for this circuit are supply‐rise‐time independent. The structure has been implemented in a 0.18‐μm CMOS technology, occupying an active area of 48 × 40 μm2.

show abstract

A Scalable Delay‐Expanding Technique for Low‐Area On‐Chip Power‐On Reset Circuits

Mansoury,

Saeedi,

Atarodi

2024

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

An ultra-low quiescent current power-on reset circuit with DDPG method

He,

Wu,

Xie

et al. 2024

AEU - International Journal of Electronics and Communications

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A low quiescent current power-on-reset circuit with configurable trip voltage

Cited by 2 publications

References 19 publications

A Scalable Delay‐Expanding Technique for Low‐Area On‐Chip Power‐On Reset Circuits

A Scalable Delay‐Expanding Technique for Low‐Area On‐Chip Power‐On Reset Circuits

An ultra-low quiescent current power-on reset circuit with DDPG method

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