A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

“…In a conventional SAR ADC, linearity characteristic deteriorates as input/reference voltage reaches the supply rail due to imperfect switching of the DAC circuit. This will confine full-scale and dynamic range of the converter [10,11]. On the other hand, mismatches of capacitor bank and process, voltage and temperature (PVT) sensitivity of DAC should be compensated by hard or soft calibration [12][13][14].…”

“…Furthermore, the implemented circuit can be easily reconfigured for different sets of sampling rate and resolution just by modifying the controller. The cyclic ADC [11,18,19] and more especially the two-capacitor (2C-DAC) SAR [20,21] can be regarded as the analogous topologies to the DLSAR architecture. However, all these topologies employ analog circuitry while the proposed DLSAR ADC is implemented by default building blocks of the conventional SAR architecture, that will be discussed shortly.…”