A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application

John, J.P.; Ilderem, V.; Park, Changhae; Teplik, J.; Klein, K.; Cheng, Shui-Ming

doi:10.1109/vlsit.1996.507843

Cited by 10 publications

(3 citation statements)

References 3 publications

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“…The process flow for LAC MOSFETs is identical to that of conventional MOSFETs except for the threshold adjust implant, which is done through a tilted angle implantation from the source side, after the gate electrode formation [16]. Pocket implant parameters such as dose, energy, and tilt angle are optimized in order to maximize the device performance parameters.…”

Section: Simulation Setupmentioning

confidence: 99%

The Effect of LAC Doping on Deep Submicrometer Transistor Capacitances and its Influence on Device RF Performance

Narasimhulu

Desai

Narendra

et al. 2004

IEEE Trans. Electron Devices

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Abstract-In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in , max , and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.Index Terms-Analog, drain voltage noise spectral densities, lateral asymmetric channel (LAC), RF CMOS.

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Section: Simulation Setupmentioning

confidence: 99%

The Effect of LAC Doping on Deep Submicrometer Transistor Capacitances and its Influence on Device RF Performance

Narasimhulu

Desai

Narendra

et al. 2004

IEEE Trans. Electron Devices

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“…The devices used in this study are fabricated using the low-voltage graded-channel MOSFET (LV-GCMOS) process discussed in [11]. This process is designed for operation in the V regime.…”

Section: Device Fabricationmentioning

confidence: 99%

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

John

Teplik²,

Hildreth³

et al. 1998

IEEE Trans. Semicond. Manufact.

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Maintaining tight threshold voltage (V T V T V T ) control for a low-voltage CMOS process is critical due to the large impact of V T V T V T on circuit performance at low power supply voltages. In this paper, PMOS V T V T V T was shown to be sensitive to poly gate thickness and BF + + + 2 source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS VT VT VT . We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two.

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“…Ion implantation technique is the most widely used for reduced C bc of GaAs HBTs, but it is not a viable technique for InP-based HBTs [1], [2]. Regrown base [3], and L-shaped base electrodes [4] are used for reduction of R b . The transferred substrate technique, which can minimize the C bc , yields an HBT with fmax in excess of 1 THz [5].…”

Section: Introductionmentioning

confidence: 99%

Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Borse

Jha

et al. 2002

IEEE Trans. Electron Devices

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Abstract-Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes.

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A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application

Cited by 10 publications

References 3 publications

The Effect of LAC Doping on Deep Submicrometer Transistor Capacitances and its Influence on Device RF Performance

The Effect of LAC Doping on Deep Submicrometer Transistor Capacitances and its Influence on Device RF Performance

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

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