A Low-Voltage, Highly Linear, and Tunable Triode Transconductor

Kuo, Ko-Chi; Wu, Hsing-Hui

doi:10.1109/edssc.2007.4450138

Cited by 8 publications

(1 citation statement)

References 20 publications

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“…7). Such designs are known to achieve very high linearity [14, 15]. The transistors

M_{1}

and

M_{2}

operate in triode region where their drain current

I_{D}

is linearly related to the gate‐source voltage

V_{GS}

I_{D} = k_{n} ()(, ()(, V_{GS} - V_{th}) V_{DS} - \frac{V_{DS}^{2}}{2})

Additionally, the drain current is strongly dependent on the drain‐source voltage.…”

Section: Design Of the Analogue Equalisermentioning

confidence: 99%

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Buhr

Kreissig

et al. 2020

IET Circuits, Devices & Systems

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This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m-C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10 −12) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors' knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

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“…7). Such designs are known to achieve very high linearity [14, 15]. The transistors

M_{1}

and

M_{2}

operate in triode region where their drain current

I_{D}

is linearly related to the gate‐source voltage

V_{GS}

I_{D} = k_{n} ()(, ()(, V_{GS} - V_{th}) V_{DS} - \frac{V_{DS}^{2}}{2})

Additionally, the drain current is strongly dependent on the drain‐source voltage.…”

Section: Design Of the Analogue Equalisermentioning

confidence: 99%

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Buhr

Kreissig

et al. 2020

IET Circuits, Devices & Systems

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Highly linear CMOS triode transconductor for VHF applications

Jendernalik

Szczepański

Koziel

2012

IET Circuits Devices Syst.

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A high-speed, fully balanced complementary-symmetry metal-oxide-semiconductor (CMOS) triode transconductor is presented. The proposed approach exploits a pseudo-differential-pair triode configuration with a simple adaptive circuit stabilising the drain-to-source voltages of metal-oxide-semiconductor (MOS) transistors. Since no additional active circuits (apart from the resistors made of the cut-off MOS devices) and no feedback loop are used, linearisation improvement is obtained without compromising bandwidth and power consumption. The non-linearity because of the mobility degradation is also compensated. The transconductance of the proposed transconductor can be up to several times higher than for the classical topologies with no extra power consumption. As an example, the transconductor is used to design sixth-order elliptic band-pass filter in the very-high-frequency (VHF) range, simulated in a 0.35 mm CMOS process (AMS).

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A highly linear basebandG_m—Cfilter for WLAN application

Liu

Gong²,

Yin³

et al. 2011

J. Semicond.

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A low voltage, highly linear transconductance-C (G m -C ) low-pass filter for wireless local area network (WLAN) transceiver application is proposed. This transmitter (Tx) filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency. By utilizing pseudo-differential linear-region MOS transconductors, the filter IIP 3 is measured to be as high as 9.5 dBm. Fabricated in a 0.35 m standard CMOS technology, the proposed filter chip occupies a 0.41 0.17 mm 2 die area and consumes 3.36 mA from a 3.3-V power supply.

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A Low-Voltage, Highly Linear, and Tunable Triode Transconductor

Cited by 8 publications

References 20 publications

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Highly linear CMOS triode transconductor for VHF applications

A highly linear basebandG_m—Cfilter for WLAN application

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A Low-Voltage, Highly Linear, and Tunable Triode Transconductor

Cited by 8 publications

References 20 publications

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Highly linear CMOS triode transconductor for VHF applications

A highly linear basebandGm—Cfilter for WLAN application

Contact Info

Product

Resources

About

A highly linear basebandG_m—Cfilter for WLAN application