A Machine Learning Approach to Predict Timing Delays During FPGA Placement

Martin, Timothy J.; Gréwal, Gary; Areibi, Shawki

doi:10.1109/ipdpsw52791.2021.00026

Cited by 7 publications

(2 citation statements)

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“…Finally, their provided timing model did not consider the cascaded multi-site macros in practical designs. Other previous works like machine learning-based solution [47] and look-up table-based solutions [29] [48], which are not open-source, rely on the large dataset provided by industry and detailed hyperparameter tuning.…”

Section: Implementation Of Sta-dependent Phases a Regression-based Ti...mentioning

confidence: 99%

“…• Timing estimation accuracy: The timing estimation model is relatively optimistic without considering a few of congested regions overlapped with the critical paths, as evaluated in Section IV-A. This problem is noticeable for benchmark DigitRecog [52] and MemN2N [55], which might be resolved by machine-learning-based timing estimation like [47] in the future. Moreover, the timing analysis and optimization at floorplanning stage might be insufficient, which leads to bad start point for the later placement flow and make it extremely hard to reach the optimal placement.…”

Section: B Comparison With Vivadomentioning

confidence: 99%

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AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

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To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

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Section: Implementation Of Sta-dependent Phases a Regression-based Ti...mentioning

confidence: 99%

Section: B Comparison With Vivadomentioning

confidence: 99%