A Manual on ASIC Front to Back End Design Flow

Rodrigues, Joachim Neves; Kamuf, Matthias; Hedberg, H.; Öwall, Viktor

doi:10.1109/mse.2005.9

Cited by 11 publications

(3 citation statements)

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“…DTA-PUF aims to jointly consider the inherent complexity of timing error manifestation with the intrinsic chip variations, proposing a new approach that inseparably intertwines PUF performance with dynamic error behaviour of pipelined cores. Our PUF implementation and evaluation rely on detailed post-layout gate-level simulation which is one of the most accurate, pre-fabrication steps of the standard ASIC flow used in industry [52]. Figure 3 shows the proposed PUF design for generating the challenge-response mechanism.…”

Section: Proposed Software Pufmentioning

confidence: 99%

“…(ns) It is important to note that such a technique does not provide a perfectly accurate representation of real hardware, however, it sufficiently reflects the actual timing behaviour of circuits after fabrication as recently indicated [37,64]. Nonetheless, such a delay representation is based on detailed post-layout gate-level simulation which is among the final steps of the typical ASIC design flow used in industry [52]. In general, in the IoT regime where million of devices are connected to the Internet, there is a need to address hardware security challenges and validate the effectiveness of security protocols at design cycle, i.e.…”

Section: Clock Periodmentioning

confidence: 99%

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DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

Tsiokanos

Miskelly

et al. 2021

J. Emerg. Technol. Comput. Syst.

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In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required processing effort, we systematically select instruction sequences that maximise error-rate. The application to a post-layout pipelined floating-point unit, which is implemented in 45 nm process technology, demonstrates the effectiveness and practicability of our PUF design. Finally, DTA-PUF requires up to 50× fewer instructions than existing software processor PUF designs, limiting processing costs and resulting in up to 26% power savings.

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Section: Proposed Software Pufmentioning

confidence: 99%

Section: Clock Periodmentioning

confidence: 99%

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

Tsiokanos

Miskelly

et al. 2021

J. Emerg. Technol. Comput. Syst.

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“…Most of the existing CaSeAs suffer from carry propagation in their internal RCA blocks, and few have area constraint problems. From the study of previous work on CaSeA, the cell regularity and uniform structure of the final design plays a vital role in the physical design of ASIC [20][21][22]. The back-end design can be made simpler with cell regularity concept [23,24], and [25].…”

Section: Introductionmentioning

confidence: 99%

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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Applications of GPUs for Signal Processing Algorithms: A Case Study on Design Choices for Cyber-Physical Systems

Srivastava¹,

Mittal

2021

Advances in Science, Technology &Amp; Innovation

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A Manual on ASIC Front to Back End Design Flow

Cited by 11 publications

References 0 publications

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Applications of GPUs for Signal Processing Algorithms: A Case Study on Design Choices for Cyber-Physical Systems

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