A manufacturable complementary GaAs process

Abrokwah, J.; Huang, Jane-Hwa; Ooms, W. J.; Shurboff, C.; Hallmark, Jerry; Lucero, R.; Gilbert, J.; Bernhards, B.; Hansell, G.

doi:10.1109/gaas.1993.394486

Cited by 36 publications

(7 citation statements)

References 4 publications

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“…This will include single and dual-input macromodels for delay and output transition times with respect to each input. We also plan to use this technique for the CGaAs [1] technology.…”

Section: Discussionmentioning

confidence: 99%

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Chandramouli¹,

Sakallah²

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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“…This will include single and dual-input macromodels for delay and output transition times with respect to each input. We also plan to use this technique for the CGaAs [1] technology.…”

Section: Discussionmentioning

confidence: 99%

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Chandramouli¹,

Sakallah²

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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“…Similarly, to fully profit from reduced-feature-size and reduced-voltage scaling, complementary III-V technologies are most effective. Recently, InGaAs [125] and GaAs [126] complementary technologies have been introduced.…”

Section: Modementioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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“…CGaAs, a complementary heterostructure-insulated-gate FET technology, has been described elsewhere [7][8][9]. A sketch of the device structure is shown in Fig.…”

Section: Complementary Gaas Technology Descriptionmentioning

confidence: 99%

Overview of complementary GaAs technology for high-speed VLSI circuits

Brown

Bernhardt

LaMacchia

et al. 1998

IEEE Trans. VLSI Syst.

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A self-aligned complementary GaAs (CGaAs TM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01µW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC TM-architecture microprocessor. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application of the CGaAs technology.

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A manufacturable complementary GaAs process

Cited by 36 publications

References 4 publications

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Tunnelling-based SRAM

Overview of complementary GaAs technology for high-speed VLSI circuits

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