A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

Lien, W.Y.; Yeh, Wen-Kuan; Li, C.H.; Tu, K.C.; Chang, I.H.; Chu, H.C.; Liaw, W.R.; Lee, H.F.; Chou, Hong-Shing; Chen, C.Y.; Chi, Min-Hwa

doi:10.1109/asmc.2002.1001565

Cited by 9 publications

(1 citation statement)

References 6 publications

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“…In past years, many groups have been studied root cause of STI stress and its solution to reduce the dislocation. In a general view of process integration of STI, STI profile, liner material, gap-fill material, and annealing play an important role in dislocation generation [3][4][5][6][7][8]. However, the most STI related processes are strong dependent on the device characteristics.…”

Section: Introductionmentioning

confidence: 99%

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Kim

Yoo

Chang

2007

SSP

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The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.

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Section: Introductionmentioning

confidence: 99%