A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation

Matoussi, Omayma; Pétrot, Frédéric

doi:10.1109/aspdac.2018.8297365

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…IR-level back-annotation: Several groups have proposed mappings from binary to compiler IR (thus, only considering backend optimization) [8,21,32], or only from IR to source (thus, only considering high-level optimization), as in [31]. Both of these approaches have their place next to a full binary-to-source mapping as proposed here, since they can be used as fallback solutions, and are likely necessary to realize precise source-level cache models.…”

Section: Related Workmentioning

confidence: 99%

WCET Analysis meets Virtual Prototyping

Becker

Pazaj

Chakraborty

2019

Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems

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In this paper we discuss the problem of relating machine instructions to source level constructs, and how it has been addressed in the domains of Virtual Prototyping (VP) and Worst-Case Execution Time (WCET) analysis. It has been handled in different ways, although the goals and requirements between both domains are not far from another. This paper shows that there exists a mutual benefit in exchanging solutions between the two research domains, by demonstrating the applicability and utility of VP methods for WCET analysis, and highlighting their shortcomings. After an evaluation of existing methods, we carefully rework and combine them to a sound and generic mapping algorithm for source-level WCET analysis. As a result, we obtain WCET estimates that outperform classic binary analyzers especially under moderate compiler optimization. Our approach is based on hierarchical flow matching, control-dependency-and dominator-homomorphic maps, and dominator lumping to soundly fill the gaps in the mapping. WCET estimation is performed using Model Checking, which maximally exploits the information available in the source, and highlights remaining weaknesses in the mapping methods. Last but not least, we discuss further chances of synergy between both research communities which could enable support for more complex microarchitectures with caches, pipelines and speculative execution in both source-level WCET analysis and VP. CCS Concepts • Software and its engineering → Real-time systems software; Compilers; Software post-development issues;

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Section: Related Workmentioning

confidence: 99%